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54 DESIGN007 MAGAZINE I APRIL 2019 etary information about the modeled circuit since no process or circuit design information is disclosed. The IBIS models are accurate since nonlin- ear aspects of I/O structures as well as pack- age parasitics, on-die termination (ODT), and ESD structures are considered in the model parameters. More recently, power-aware mod- els have been specified to combine signal in- tegrity (SI) and power integrity (PI) simula- tion. Since the IBIS is behavioral, the simula- tion time for a model can run some 25 times faster than a structural model such as that used in SPICE. In addition, IBIS does not have non-convergence issues encountered in SPICE models that prevent the simulator from reach - ing a valid solution within a certain number of iterations. Now, most EDA vendors support the IBIS specification as the defacto simula- tion standard. IBIS models for many devices are available as free downloads from IC vendor support pag- es. IBIS provides the following: • Faster simulation speed • A large variety of I/Os in a single IBIS file so that easy system model simulation is possible • The inclusion of signal integrity specifications, such as input logic thresholds, overshoots, etc. • Power-aware properties introduced to provide simultaneous SI/PI analysis • Elimination of non-convergence • Strong support from virtually all EDA vendors • Backward compatibility with models created under previous IBIS standards At its core, a CMOS IBIS model (Figure 2) uses only a few tables of data to represent the behavioral characteristics of a buffer. Two sets of I-V tables represent the I DS versus V charac- teristics of the pull-down and pull-up transis- tors, showing the dynamic impedance of the buffer. The switching behavior of the buffer is revealed through a set of V-T tables that cap- ture the rising and falling edge transitions of the buffer driving resistive test loads. The ca- pacitance of the buffer and the package RLC are also quantified. This information, plus the transmission line characteristics, provides an accurate model for SI simulation, but it lacks behavioral characteristics necessary for PI sim- ulation. One of the major upgrades in the IBIS version 5.0 specification was the introduction of additional data tables to model buffer power characteristics (not shown). Models contain- ing these data are known as power-aware IBIS models. Let's look at a practical example of how to implement a transmission line simulation Figure 2: Building blocks of a CMOS buffer IBIS model.

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