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APRIL 2019 I DESIGN007 MAGAZINE 55 using the IBIS model. I/O buffer and drive strength selection can be analyzed in pre-lay- out simulation. A vendor-provided IBIS mod- el should contain all available drivers for each model, and may, for example, include buffer models with 8 mA, 12 mA, and 16 mA drive current. The mid-level 12-mA driver is general- ly required unless there is a long transmission line with multiple loads. This may be the case on a motherboard when driving a number of DIMM modules, for instance. The schematic description that includes the stackup definition, arrangement of a network, its nodes, sequence, connecting transmission lines and vias is generically referred to as the interconnect topology. To avoid signal quality and timing issues and minimize manufacturing costs, thorough topology analy- sis is critical to the successful im- plementation of a high-speed in- terconnect. Ideally, this analysis should be done up-front before placement and routing. Topology optimization involves: • Selecting an optimal topology style for signal integrity, timing, and EMC • Shortening traces and stubs to their critical length or shorter where possible The most basic topology is a simple point-to-point intercon- nection between a driver and a receiver (Figure 3). This topolo- gy is commonly used for busses or otherwise grouped traces. A good example of this would be the data banks of DDRx memory. Left un- terminated, these traces may be too long (more than 1/10 rise time), and reflections become problematic. Figure 3 also illustrates a Xilinx, Virtex 4 transceiver driving a DDR2 data signal into a long, 52.2-ohm transmission line. Ini- tially, the signal was simulated with no series termination, resulting in the red waveform in Figure 4. The green waveform represents the terminated transmission line. The impedance of the trace is extremely im- portant, as any mismatch along the transmis- sion path will result in a reduction in signal Figure 3: DDR2 data signal with a series terminator. (Source: HyperLynx) Figure 4: Ringing of the data signal due to reflections. (Source: HyperLynx)