Issue link: https://iconnect007.uberflip.com/i/1101604
56 DESIGN007 MAGAZINE I APRIL 2019 quality and possibly the radiation of noise. Mismatched impedance causes signals to re- flect back and forth along the transmission line, which results in ringing at the load (Fig- ure 4). The ringing reduces the dynamic range of the receiver, eats into the noise budget, and can cause false triggering due to non-mono- tonic edges. Reflections occur whenever the impedance of the transmission line changes along its length. This can be caused by unmatched driv- ers/loads, layer transitions, different dielectric materials, stubs, vias, connectors, and IC pack- ages. By understanding the causes of these re- flections and eliminating the source of the mis- match, a design can be engineered with reli- able performance. For the perfect transfer of energy and to eliminate reflections, the imped- ance of the source must equal the impedance of the transmission line. It is one thing to perfectly match the imped- ance and delay of the transmission lines, but using mainstream PCB layout software, un- fortunately, one really has no idea what the driver impedance is, let alone the capability to match the driver to the impedance of the trans- mission line. The iCD Termination Planner ad- dresses this issue (Figure 5). First, the attributes required to determine the source impedance of the driver are extract- ed from an IBIS model I-V curves. Then, the required series termination resistance is calcu- lated based on a distributed system to match the transmission line impedance for the select- ed stackup layer. The number of loads on the transmission line also has an impact on the re- quired value of series termination, as the IC in- put inductance and capacitance tend to roll off the signal rise time. This can be adjusted from 1–6 loads and automatically compensated for in the calculation. If you do not have access to a board-level simulator, then this is a good op- tion to easily avert ringing. Modeling complex PCB designs does not have to be time-consuming and difficult. The topo- logy can generally be automatically extracted from the PCB layout into a free-form schemat - ic, providing all the transmission line, via, and stackup information required. The designer only needs to select the IBIS driver and load models plus a stimulus in the form of a set frequency or a pseudorandom bit stream (PRBS) to simulate Figure 5: Matching a DDR3 driver IC to the transmission line. (Source: iCD Termination Planner)