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MAY 2019 I DESIGN007 MAGAZINE 25 throughout the design process using the same consistent management tool. Also, the reuse of constraints from a previous proven design not only ensures consistent rules but also minimiz- es the possibility of errors. Net classes are used to organize and speed up the definition of routing constraints for nets with similar properties. For each net class, the layers allowed for routing, the corresponding trace width range for these layers, and the via types allowed can be defined. For differential pairs, a layer-dependent differential pair gap can be defined based on the calculated imped- ance to ensure uniform impedance across all layers. The proper grouping and definition of net classes and constraint classes in the early stag- es of the design process simplifies constraint definition and management significantly. Grouped constraints can increase layout effi- ciency, reducing design time, and, ultimately, lower PCB design costs. With DDRx design, it is also a requirement to assign layer sets to data lanes/strobes and ad- dress, command, and control (ACC) and their associated clocks to ensure matched propa- gation delay. Signals within a group should be routed on the same layer with each path having the same via count. Even if the trace widths are adjusted on each layer, so as the impedance is identical, the propagation speed of microstrip (outer layer) is always faster than stripline (inner layer), typically by 13–17% (Figure 3). The speed of propagation of dig- ital signals is independent of trace geometry and impedance and is solely determined by the dielectric constant of the material the electro- magnetic energy propagates in. The higher the signal frequency with which the designer must contend, the more compli- cated will be the PCB design. Complex PCB de- signs require deep knowledge and experience and simulation tools. However, it is not always necessary to route traces as short as possible, differential signals as close as possible, or to avoid crosstalk as much as possible. Rather, it depends on the signal's significance. Basically, the designer must know which are the sensi- Figure 2: Constraints planning at the schematic level (PADS Professional).