Issue link: https://iconnect007.uberflip.com/i/1114420
26 DESIGN007 MAGAZINE I MAY 2019 tive parts in the circuit or where problems due to reflections and crosstalk can occur. With this knowledge, good placement of the devic- es can be made. Because placement is such an important step in high-speed design, the de- signer will do well always to keep it and the return current in mind. With higher frequencies and faster transition times, the digital system timing budget is also of the utmost importance. The timing bud- get is the account of timing requirements nec- essary for a system to function properly. For synchronous systems to work, timing require- ments must fit within one clock cycle. A tim- ing budget calculation involves many factors, including setup and hold time and maximum operating frequency requirements. By calculat- ing a timing budget, the limitations of conven- tional clocking methods can be seen. This data can then be translated into routing design con- straints. The first step in establishing the timing bud- get is to define the initial system timings. To do this, one must obtain estimates of the min- imum and maximum output skew from the silicon vendors. This information is generally available in the IC datasheets. Then, define the setup and hold times for the read and write cy- cles. The timing budget for each component is then calculated given a certain margin. What- ever is left over (if anything) can then be allocated to the board- level interconnect design. This is the only factor that PCB de- signers can influence. If there is no margin left for the intercon- nect, then the silicon numbers need to be retargeted, or an easier solution might be to de- crease the clock speed. This is why a shoddy design may work at a low frequency but not at full speed. Timing is everything in high-speed design. In conclusion, PCB designers need to understand the under- lying high-speed design issues of the design based on simu- lation and then translate these into corresponding design constraints. Con- straints can always be altered on the fly if a particular constraint is too tight, providing the designer can justify the easing of the speci- fication and that the product is still manufac- turable. Key Points: • The key methodology is to understand the underlying high-speed design issues and then translate these into corresponding design constraints • High-speed design constraints are based on pre-layout simulation • Constraint reuse is limited by net and group naming conventions; if you are consistent, then porting is much easier • IPC has provided the electronics industry with guidelines for designing and manu- facturing PCBs • Entry-level EDA tools tend to rely on the skills of the PCB designer to detect possi- ble issues as they arise during the design process • A constraint-driven, correct-by-construc- tion approach is required for complex designs • Constraints should be defined at the sche- matic level and flow through to the layout process Figure 3: Relative signal propagation of microstrip and stripline (iCD Design Integrity).