Issue link: https://iconnect007.uberflip.com/i/1114420
42 DESIGN007 MAGAZINE I MAY 2019 ment. They're driving all the way down to the lot size of one—a customizable manufacturing process that can cost-effectively produce one board. Again, a lot of that has to be optimized like IC, but the cost associated with failure and implementation is lower. Shaughnessy: One of the overarching themes here seems to be the management of all these rules. You may have rules for signal integrity, power integrity, and the fabricator's etch-back rules, etc., but how does anyone manage all of this? Wiens: It requires cross-domain awareness. The engineer defining the rules for signal integrity has to be aware of the manufacturing process that's going to be used. Are they going to be doing microvias or back drills on through-hole vias? They could define a constraint that says every via has to be back drilled because ev- erybody knows that unused vias are noisy, so back-drill every via. There's a cost associated with that, and is that necessary? Also, if you're drilling vias, the deeper the via, the more the bit is going to wobble. That's a tolerance issue. Shaughnessy: A fabricator might say, "Here's how we do stackups," and the EDA company has to turn that into a constraint. Wiens: Stackups are another item that can be defined in a variety of tools from the manu- facturing side. Of course, they can put them in Valor. That's a direct transfer back to the de- signer. They might send them to us in other formats or tools, so we've had to add capabili- ties to import that into our constraint environ- ment to avoid having to re-enter rules like that. The stackup that you're using absolutely im- pacts the performance; it changes every single performance constraint. That's where reuse comes in, knowing what their most cost-effec- tive stackups look like and picking from those when you define your constraints up front for performance. The Mentor Xpedition constraint editor.