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AUGUST 2019 I PCB007 MAGAZINE 43 the non-planar filling of plated through-holes. Via hole plugging is synonymous with the pla- narization of blind and buried vias as well as through-holes. Via hole plugging is applicable to HDI and microvia designs. Brushing (or pla- narization) is required to remove the excess ma- terial and create the flat surface. This technique is described in previously published papers [1 & 2] . And there are some applications where the vias will be filled by a copper electroplating pro- cess commonly known as superfilling. Superfilling or bottom-up filling of vias re- quires specialized plating processes, process controls, and plating cell set-up. This will also be the subject of a future column. For the circuit board designer, the goal is to construct an architecture with flexible designs to ensure higher I/O densities as well as lower costs and greater performance. As Figure 3 de- picts, there are four common via architectures for HDI: 1. Drill sequential lamination 2. Staggered sequential microvia build-up 3. Co-laminated any layer via stack microvia build-up 4. Stacked sequential microvia build-up Yield issues are more difficult to pin down because they depend on a number of vari- ables and are largely statistically driven (i.e., the greater the occurrence of a certain con- figuration will influence yields). Regardless, the four types of structures are used in HDI fabrication based on design constraints and routing density. PCB007 References 1. K. Andra, "Hole Plugging Technology for Multilayers and HDI Packages," EPC PCB Convention, 1999. 2. S. Kramer and M. Suppa, "Via Hole Filling and Plug- ging: Trends, Possibilities, and Limitations for Convention- al and SBU-type Fillers," IPC Printed Circuit Expo 2001. Michael Carano is VP of technology and business development for RBP Chemical Technology. To read past columns or contact Carano, click here. New Filter Enhances Robot Vision on 6D Pose Estimation A recent study was conducted by researchers at the University of Illinois at Urbana-Cham- paign, NVIDIA, the University of Wash- ington, and Stan- ford University on 6D object pose esti- mation to develop a filter to give robots greater spatial per- ception so that they can manipulate objects and navi- gate through space more accurately. While 3D pose provides location information on X, Y, and Z axes, 6D pose gives a much more complete picture. "Much like describing an airplane in flight, the robot also needs to know the three dimensions of the object's orientation—its yaw, pitch, and roll," said Xinke Deng, a doctoral student studying with Timo- thy Bretl, an associate professor in the Department of Aerospace Engineering at the U of I. Deng explained that the work was done to improve computer vision. He and his colleagues developed a filter to help robots analyze spatial data. The filter looks at each particle, or piece of image information collected by cameras aimed at an object, to help re- duce judgment errors. The study uses 6D object pose tracking in the Rao- Blackwellized particle filtering framework where the 3D rotation and the 3D translation of an object are separated. This allows the researchers' approach, called PoseRBPF, to efficiently estimate the 3D trans- lation of an object along with the full distribution over the 3D rotation. As a result, PoseRBPF can track ob- jects with arbitrary symmetries while still maintaining adequate posterior distributions. (Source: University of Illinois)

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