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90 PCB007 MAGAZINE I AUGUST 2019 Article by Ed Hickey, Mike Catrambone CADENCE DESIGN SYSTEMS and Joan Tourné NEXTGIN TECHNOLOGY Editor's Note: This article is part three of a se- ries on vertical conductive structures. Click here to read Part 1 and Part 2. As design complexity and density increases, it sometimes requires the designer to leverage different via technologies to successfully route into larger pin count devices while maintain- ing the highest level of signal integrity. Using through-hole vias can take up a lot of valuable board space; moving to smaller blind vias re- duces the via size but will require larger buried vias to complete the connections deeper in the board. Another costly alternative is using ev- ery layer interconnect (ELIC) technology with each layer pair having its own copper-filled, la- ser-drilled microvias. Stacking these microvias on top of each other between layer pairs can extend the connection between any two layers in the board. These via technologies may suc- cessfully route the design but could cause the layer count to rise, and if not done correctly, could lead to signal integrity issues. New vertical conductive structure (VeCS) technology can reduce layer count and im- prove signal integrity without the need for se- quential technologies. VeCS is different than traditional through-hole vias, microvias, and ELIC designs, which are more expensive and require a high number of laminations, drilling, and plating cycles to build up a reasonable number of layers. Using VeCS combines rout- ing channels for better utilization of the chan- nel, escaping out large pin count devices. The larger routing channels allow more routes to escape with a more reliable/solid plane refer- ence without the swiss-cheese effect normally seen with other via technologies. In Allegro 17.2, VeCS structures are nothing more than a mechanical symbol that can be free-placed or placed inside of a ball grid ar- ray (BGA) field to take advantage of this new routing escape technology. No major changes were required to support these new structures in Allegro PCB Designer except for a manufac- Vertical Conductive Structures, Part 3: Design Tool Techniques

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