Issue link: https://iconnect007.uberflip.com/i/1156271
AUGUST 2019 I PCB007 MAGAZINE 99 identify the blind depth of the VeCS-2 structure – It is not required to define the entire stackup; the start/stop subclass names must match the target design • Padstack geometry definition on start/stop layer drive the blind depth when placed in the design Setting Up Design Rules Padstacks With the advancements made in the 17.2 Padstack Editor, there are no special design rules required to successfully use a VeCS struc- ture in the layout. • Plated slots: Adjacent layer keepout for mechanical drill overshoot clearance for VeCS-2 • Non-plated hole/slot (slot separator): Keepout on all layers for clearance to the non-plated hole or slot – Utilizing by-layer keepouts and adjacent layer keepouts for VeCS-2 structures Pin Properties Applied in the Layout Placing the VeCS structure in the layout will produce DRC errors between the plated slot and non-plated hole/slot (slot separator) pins, which is expected. To eliminate these DRC er- rors, the designer must apply NO_DRC prop- erties to the pins of the VeCS structure. This property can be added upon placing the first VeCS structure and a simple copy this struc- ture to all the required locations in the design. Fabrication Output VeCS structures in Allegro PCB design- er should work directly out of the box ex- cept when moving to VeCS-2 structures (blind depth). To support VeCS-2, a manufacturing output change was made to generate the ap- propriate drill files for blind/buried drills and slots (Figures 20 and 21). This manufacturing output change was made in 17.2 QIR5 (S031) in December 2017. PCB007 Ed Hickey is product engineering director at Cadence Design Systems. Mike Catrambone is senior principal product engineer at Cadence Design Systems. Joan Tourné is CEO of NextGIn Technology BV. Figure 20: Example of drill/route table. Figure 21: 3D view of VeCS as solid and in cross-section.