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94 PCB007 MAGAZINE I AUGUST 2019 For the inner layer, we have a similar setup (Figure 4). The rules are less complex. We have to make sure we adopt the misregistration us- ing the pad such that we always have a con- nection between inner layer copper and plat- ing. We also want to have an overlap with the slot enough to accommodate for the misregis- tration and guarantee a contact between pad and plating. Typically, half of the pad will be routed away when forming a slot. The exam- ple of a reduced pad size is demonstrating that smaller pads are possible, but as with drilling, it could be pulled out when routing the slot. In Figure 4, we used different pad shapes and dimensions. Choose the one that works best for you. Having no pad is an option as well. When trace width of the horizontal trace and vertical trace are close, then small misregistration can create an open when the second route and in - ner layer are not aligned with the design margin. We do not have the problem etching away plating at the inner layer stage. The situation for Pad A will work; the only critical item is that the DRC function in your CAD system has to take into account the plating. This is typical- ly defined by the pad. The annular ring dimension we have to respect is 0.1 mm at a minimum to prevent break-out. Consult you PCB fab- ricator before starting the design on dimensions/design rules. Non- functional pads can be removed as well in VeCS designs. In the following section, we de- scribe how Cadence implemented VeCS into the Allegro design sys- tem. The difference you see com- pared to the design rules described in the first section are that we use a second drill with re- spect to a second route. A second drill can be used when space allows. VeCS Structure Overview in Cadence Allegro VeCS structures are built as mechanical sym- bols using pins and vias in the Allegro Sym- bol Editor. These mechanical symbols are then placed in the design as needed for routing, no need to add VeCS structure symbols to the schematic. Standard VeCS structures can utilize through-hole drill features (VeCS-1) but also be constructed using blind drill features (VeCS-2). The following is a description of the different entities in a VeCS Structure (Figure 5): • Plated slot defined as pins – Pins without logic pin number assignment • Non-plated slot separators defined as pins – Slotted hole could be used for finer pitch BGA pin fields • Connection vias defined as a via with stub traces – Vias adopts BGA pin net once stub trace endpoint contacts the BGA pin center – To expedite creation, the connection via/cline stub arrangement could be created in the layout then imported into the Symbol Editor using a sub-drawing • Arrange the different objects to form the final VeCS structure • Note: The pad and drill sizes used for the pins/vias are driven by its application in the design. (i.e., BGA pitch and ball pad sizes) Figure 4: Pad definition, inner layer. Figure 5: The different entities in a VeCS structure.