Issue link: https://iconnect007.uberflip.com/i/1174596
76 DESIGN007 MAGAZINE I OCTOBER 2019 0N and XYZ-0P where the "0" would be incre- mented if these nets are part of a bus. For pin-pair definition, there should be op- tions to do this automatically, controlling pin- to-pin sequencing manually or via simulation, to save us additional time when defining com- plex pin-pair assignments, such as multi-chip DDR arrangements. Having the ability to save a pin-pair assignment to a constraint template (Figure 4) and then apply it to all nets of like types can save hours of work. A bonus is the ability to have your signal integrity tool create a topology definition from your simulation work, export to your rule entry environment, and then apply this template to appropriate nets. An additional benefit to constraint templates is that when a change is made to the parameters in the template, it's au - tomatically applied to the nets to which it has been assigned. 2. Interactive Routing Typically, the first task in rout- ing a PCB is to create the fanouts for components, assuming de- sign rules have been created. Ev- ery PCB design tool has the abil- ity to place fanouts by hand with the simple process of starting a route and ter- minating with a via. This time-consuming and labor-intensive phase of the design process can easily be automated with the proper tool. To- day's designers should not be doing this step manually. Modern tools provide fanout setup options (Figure 5). Designs with 1,000+ power and ground pins can be fanned out in seconds with the same quality as hand-routing. For finer control of your fanouts, or for com- plex via structures (more than one via per pin), you can manually create fanouts for cer- tain pins or an entire component. Then, us- ing copy and paste, you can replicate those via structures on other pins or components. Once you are satisfied with the critical fanouts, you Figure 4: CES constraint template. Figure 5: Auto fanout setup.