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62 DESIGN007 MAGAZINE I JANUARY 2020 Wafer-level Packaging WLP technology is commonly utilized to ac- commodate die elements having very high pin count. Developers have found that by redistrib- uting terminals inside and/or outside the die perimeter, they can accommodate the redistri- bution on the die terminals to a wider substrate terminal pitch that is more compatible with an organic substrate or PCB circuit routing capa- bility. Silicon wafers are commonly utilized for a broad range of these single- and multi- ple-die packaging applications, and, although considered an emerging technology, even glass panels are expected to be a viable low-cost al- ternative to the silicon material. Even though the silicon- and glass-based materials are con- sidered to be an ideal match for HD semicon- ductor packaging, glass-reinforced B-T epoxy material has been successfully used in manu- facturing package substrates for a significant portion of single- and multiple-die packaging markets. Examples of FIWLP and FOWLP are illustrated in Figure 2. Preparing die elements for direct chip attach- ment (flip-chip) to the wafer-level base requires several metalization procedures. While the die elements remain in the wafer format, they are subjected to a rather complex sequence of plat- ing and chemical etching processes to form the conductors and terminal lands required for sol- der bump or sphere attachment. The first process step employs a sputter- ing procedure to furnish a barrier metal and enable the deposition of a copper seed layer over the active surface of the wafer. A coating of photoresist is then applied over the wafer surface, imaged and subjected to a secondary copper electroplating process to provide the interconnect pattern. After copper plating to form the interconnect pattern and the barrier and seed layer, metalization is chemically re- moved, leaving only the copper redistribution layer (RDL) ready for passivation and further imaging processes to expose the copper con- tact pattern for terminal formation. Following terminal formation, the die ele- ments are singulated from the wafer format and transferred to systems specifically de- signed for precise die placement onto the sub- strate or interposer panel. 2D WLP system-lev- el microcircuits have wide appeal when pack- aging products require the use of multiple bare die elements from several sources. The semi- conductor die elements will be mounted onto the base material facedown (flip-chip) to ac- commodate reflow solder or alternative join- ing technologies. Passive elements may also be placed onto the interconnect substrate while in the wafer format. System-level Packaging Many companies have realized that integrat- ing mature multiple-die elements into a 2D or 3D configured package proves to be superi- or to a single, multiple-function die (system- on-chip, or SoC) concept because it minimiz- es risk and significantly reduces both develop- ment time and cost. Although integrating sev- eral semiconductor functions onto a single die element may appear to provide a viable solu- tion for companies producing products in very high volume, the cost and time required to de- velop the multiple function SoC semiconduc- tor have often proved excessive. The challenge the developer faces is selecting the chipset that will meet the designated functional goals and Figure 2: Comparing fan-in and fan-out WLP variations.

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