Issue link: https://iconnect007.uberflip.com/i/1199133
64 DESIGN007 MAGAZINE I JANUARY 2020 of the host PCB, more efficient circuit routing, fewer circuit layers, and improved power utili- zation and ground distribution. Key Planning Issues for 2D, 3D, and 2.5D Packaging A great deal of progress has been made in semiconductor package process refinement and system development; however, method- ologies can vary significantly. Issues that will need to be resolved before initiating package development include: • Selection of suitable semiconductors for multiple-die packaging • Establishing reliable sources for semiconductor elements • Specifying physical and environmental operating conditions • Defining package design constraints and process protocols • Stipulating electrical test method and post-assembly inspection criteria Upcoming Presentation Vern will be conducting a half-day tutorial workshop on "PCB Designers Guide to Flip- Chip, WLP, FOWLP, and 2D, 2.5D, and 3D Semiconductor Package Technologies" at IPC APEX EXPO 2020 to be held at the San Di- ego Convention Center on Monday, February 3. This course addresses the design and as- sembly challenges for developing and imple- menting flip-chip and multiple function sys- tem-in-package (SiP) technology. To register for this timely tutorial workshop program, visit www.ipc.org. DESIGN007 Vern Solberg is an independent technical consultant based in Saratoga, California, specializing in SMT and microelectronics design and manufacturing technology. To read past columns or contact Solberg, click here. Figure 5: 2.5D interposer-enabled interconnect.