Issue link: https://iconnect007.uberflip.com/i/1199133
JANUARY 2020 I DESIGN007 MAGAZINE 23 Impedance variations along the transmission line are much more critical than a precise val- ue of impedance. A flat impedance profile is vital, and it is the PCB designer's responsibility to ensure that there is no impedance disconti- nuity due to inadequate signal routing. Unfor- tunately, differential mode propagation can be converted to common mode by any imbalance caused by impedance variation. Having a PCB fabricated to controlled im- pedance specifications does not necessarily control the impedance of your routed traces; it only controls the impedance of the inactive test coupons. The impedance test coupons do not take into account all of the possible issues that can occur throughout the maze of routing from driver to load. Only you can control the impedance of the signal interconnect. If you ex- tract the interconnect topology (Figure 3), from a PCB layout to free form schematic models, the result can be terrifying—not quite that sim- ple trace that was routed. In this case, any of the 15 individual transmission lines that form the entire interconnect can create issues if in- correctly routed. The key to controlled impedance design is to maintain consistency along the entire length of the interconnect, providing a flat impedance profile. 1. Reflections occur whenever the imped- ance of the transmission line changes along its length. This can be caused by unmatched drivers/loads, layer transitions, dissimilar dielectric materials, stubs, vias, connectors, and IC packages. Terminate transmission lines, avoid layer transitions that don't have a common reference plane, and reduce the length of stubs. 2. These reflections augment crosstalk that is caused by close coupling of signal trac- es to other structures. Designers should couple traces close to the reference plane, avoid long parallel trace segments, and increase spacing to aggressor signals. 3. There are a number of recommendations to control skew caused by a glass-weave effect. But the simplest by far is to use two combined layers of 1067-style prepreg dielectric material between the signal and Figure 3: Free-form schematic model of a DDR2 address signal (simulated in HyperLynx).