Issue link: https://iconnect007.uberflip.com/i/1199133
24 DESIGN007 MAGAZINE I JANUARY 2020 reference plane. This ensures a constant percentage of resin to glass fiber in the dielectric material and controls the com- parative propagation delay to <2 ps/12 in. 4. Signal skew also occurs when differential pairs are not properly matched. Differen- tial skew refers to the time difference between the two single-ended signals in a differential pair. Any mismatch in delay will result in changing part of the differen- tial signal into common-mode current. If there is a mismatch (e.g., on a bend), it should be balanced by lengthening the appropriate trace where the bend occurs. 5. Do not route critical signals on the outer (microstrip) layers, as these are more vulnerable to change in impedance and also difficult for the fabricator to control the plating thickness. 6. Avoid placing copper pours next to signal traces, as the copper pour will lower the impedance on the adjacent trace segment. Use three times the dielec- tric height as an effective copper pour to trace clearance rule. Establishing comprehensive design con- straints can prevent many of the above issues from occurring in the first place and will cer- tainly warn you when not enforced, depending on the level of your tool's electrical rule check- ing (ERC). (In addition, you could download the free HyperLynx DRC add-on, which can be used to identify PCB design issues affecting EMC and signal and power integrity.) Key Points • Energy is never lost but rather transforms into other forms of energy • An unmatched transmission line's energy can be transferred into heat, coupled into adjacent elements, reflected or radiated • Impedance is at the core of the methodol- ogy that is used to solve signal integrity issues • Interconnect impedance is a function of the geometry of the conductors and the dielectric constant of the material adjacent to or separating them • The most critical dimension is the ratio of trace width to height above/below the reference plane(s) • Microstrip transmission lines are more vulnerable to change in impedance, which is another good reason not to route critical signals on the outer layers • Impedance variations along the transmis- sion line are much more critical than a precise value of impedance • A flat impedance profile is vital, and it is the PCB designer's responsibility to ensure that there is no impedance discontinuity due to inadequate signal routing • Having a PCB fabricated to controlled impedance specifications does not neces- sarily control the impedance of your rout- ed traces; it only controls the impedance of the inactive test coupons • The key to controlled impedance design is to maintain consistency along the entire length of the interconnect, providing a flat impedance profile DESIGN007 Further Reading • B. Olney, "Beyond Design: Controlled Impedance Design," The PCB Design Magazine, May 2015. • B. Olney, "Beyond Design: Transmission Lines—From Barbed Wire to High-speed Interconnects," The PCB Design Magazine, May 2014. • B. Olney, "Skewed Again," The PCB Magazine, June 2013. • B. Olney, "Differential Pair Routing," The PCB Magazine, October 2011. • E. Bogatin, Signal and Power Integrity: Simplified, Prentice Hall, 2008. • H. W. Johnson & M. Graham, High-Speed Digital De- sign: A Handbook of Black Magic, Prentice Hall, 1993. • G Havermann & L. Ritchey, "[SI-LIST] Forum." Barry Olney is managing director of In- Circuit Design Pty Ltd. (iCD), Australia, a PCB design service bureau that specializes in board-level simulation. The company developed the iCD Design Integrity software incorporat- ing the iCD Stackup, PDN, and CPW Planner. The software can be downloaded at icd.com.au. To read past columns or contact Olney, click here.