Issue link: https://iconnect007.uberflip.com/i/1207026
12 SMT007 MAGAZINE I FEBRUARY 2020 The components drive the min- iaturization from a technology standpoint, and the boards drive miniaturization from a cost standpoint. Happy Holden: Yes, but what's the drive toward wafer-level packag- ing? Is it to get away from hav- ing to buy a separate component that gets assembled flip-chip- wise or something like that? From what we've been follow- ing from the ECTC conference, the wafer-level packaging sessions keep growing and growing. Bauer: The trends in wafer-level packaging are driven almost entirely by cost. The technol- ogy for doing it is like anything else; if you can minimize the cost, you're going to have an opportunity to either capture market share by reducing pricing or increasing margins. Cost is always the driver. Holden: There seems to be a major push into the electronic panel level, wafer column plat- ing, and other finishes for a level of assembly automation that includes embedded actives in the semiconductor package. _____________ Wafer-level Packaging Bauer: If you look at it from the device perspec- tive, the memory and RF companies in partic- ular have always had embedded passives on their chips. One of the biggest issues for the RF companies, especially, has been if you come up with a low-cost, silicon-integrated passive, the chip size for a GaAs chip goes down by an order of magnitude. Thus, the capacity for GaAs devices immediately goes up by an order of magnitude, and the pricing goes in the toi- let because there's suddenly a huge overcapac- ity. The gallium arsenide companies continu- ally fight against integrated passives for this reason. Holden: They deal with integrat- ing active chips that get embed- ded in the package, and die may also go on the surface, but now the actives are embedded. They supply plating and other kinds of automation for this level of integration that's growing, espe- cially in Asia, as an alternative to 3D packaging or 2.5D pack- aging. Wafer-level packaging has been going for a long while but still continues to grow. If it's wafer-level packaging, then that's the device that gets soldered onto the PCB at assembly. It doesn't go through another packaging step. It comes from the wafer and is now a com- ponent that's going to be assembled on the finished board. Is that only for the smaller number of leads? How big does wafer-level packaging go in terms of what it attempts to connect? B a u e r : To my knowledge, nobody's using wafer-level packaging to do microprocessors or large memories either. If you go to very high I/O, you still don't find it there. Johnson: Why do you suppose that is? Dana Korf: It's yield. When you get so many devices put together in a package like that, for many years, that has been known as the "known good die" problem. You put a bunch of die together, or you glob them up. One's bad, so what do you do? You throw the whole thing away. You have to know those devices are good as well as the interconnect or you throw away a lot of money for a single interconnect problem. This tends to be the problem. Bauer: I'm going to throw out a couple of some- what controversial ideas. We've talked about trying to focus on miniaturization, particu- larly 5G and high-performance technology, as well as those that will be critical for commu- nications, autonomous driving, IoT, etc. What we're very likely to find is something that the folks at Panasonic discovered back in the early Chuck Bauer