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64 SMT007 MAGAZINE I FEBRUARY 2020 Packaging technology has constantly evolved over the decades from through-hole package to SMT with ever-decreasing pitches. There are many factors that play a role in the selection of a package, such as their cost and physical size, but the role package parasitics play in package selection has not changed over many decades. For example, while the silicon designer is pre- occupied with performance issues in picosec- onds, the system designer is still struggling with performance issues in nanoseconds. This 1000X reduction in performance is caused by packages that house the silicon commonly referred to as package parasitics, and they are very different in various types of packages. Package parasitics are those undesired lead (outside the package) and bond wires (inside the package) inductance and capacitance that get in the way of the electrons trying to get to their destinations fast. Electrons are a hur- ried bunch and like to travel at the speed of light. But they are being slowed by package parasitics. Why do we need to deal with pack- ages, especially if they act like a parasite? Can't we just get rid of those packages? Why bother with parasites? To answer this question, we need to ask the next logical question: What do these packages do besides behave like parasites? They do some very useful things. For example, the packages provide power to the silicon so that the elec- trons can move around. These electrons are always in a hurry, and their fast movement gen- erates lots of heat. The packages make it pos- sible to dissipate and remove that heat so that the electrons can con- tinue to move around at high speed. If the Dealing With Package Parasitics SMT Solver by Ray Prasad, RAY PRASAD CONSULTANCY GROUP

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