Issue link: https://iconnect007.uberflip.com/i/1207026
14 SMT007 MAGAZINE I FEBRUARY 2020 Johnson: Could you give us a tutorial explain- ing what the RDL is and its purpose for those who might not be familiar with it? Korf: If you look at a traditional HDI packaging or PCB technology, you get down to 2-mil or 1.6-mil lines, and your via pads are still fairly large because you have to drop vias down into the board. If I wanted to start doing 10-mil vias into a 4-mil pad with a 1-mil wide line or less for 20-micron, 30-micron, or 40-micron layers and above, those can be done with HDI. You have to put a layer down on the outer surface so that you can now lay down that 20-micron wide line into a 100-micron pad and put your die directly onto the board. You can't afford, and you can't use that tech- nology to make the entire structure—mean- ing the entire board with six, eight, or 12 lay- ers—because of the cost and the technology doing the outer layers to redistribute the pitch to a wider pitch so that you can build it into the board. I call it RDL, taking a fine via pitch and spreading it out to go down for the rest of the board. Bauer: I agree with that. The scaling of dimen- sions at the chip level and the package level is very different than at the board level, and the RDL is a very simple term for making the two match geometrically. Holden: That's because the semiconductor companies continue to do die shrink. Korf: Exactly, That is driving down the I/O pitch, which is driving down on the I/O pitch on the board. Holden: And a smaller device turns on and off faster, which means the critical length before the required transmission line shrinks. It's all about physics. It's also like death and taxes: You can't avoid it. Korf: You have to look at the aspect ratio and the material properties of the dielectrics. Some good papers have been published on that topic in the last couple of years. You have to do a good 3D simulation of that RDL and what it attaches to so that the via doesn't break off like it used to do with BGA packages to boards. You have to look at the physics of the material and the interconnect. Johnson: Dana, that sounds like a design-time consideration. Korf: Yes, because the material is very thin, and you don't want a thick via structure. If you go back to the '80s and that period for ini- tial surface mount, we had ceramic TCE mis- match to the FR-4 that was breaking solder joints. It has resurrected where the vias will separate from each other due to CTE differ- ences from the various materials being used to have that very fine-pitch part mounted to this PCB structure. Johnson: We have these challenges in addition to packaging, of course. The semiconductor industry continues to shrink the die as much as it possibly can, and we understand why that is. It allows them to put more chips on the one wafer and increase their profit mar- gins. However, that creates this particular kind of stress at the board level. Then, the OEMs—especially, in automotive and med- ical, for example—can get more functional- ity in smaller real estate. But where we seem to have the biggest challenge at the moment is connecting those very small chips together across what we can do on a circuit board. What's going to give first? _____________ 3D Printing Dan Feinberg: Chuck, I'd like to hear your opinion on some of the recent advances in You have to look at the physics of the material and the interconnect.