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FEBRUARY 2020 I SMT007 MAGAZINE 97 ablate material at each terminal site, followed by a sequence of plating, imaging, and etching processes to complete the interface from the die to the buildup circuit layer. Microvia interface methodology is favored by a growing number of companies because they can eliminate several process steps: mate- rial dispensing, thermal curing or reflow pro- cessing, cleaning, and underfill application. Although the core-mounted semiconductor element described above is a popular tech- nique for embedding active die, a number of innovative coreless embedding methodologies have evolved. International Package Innovation Several companies in Europe, Taiwan, Japan, and Korea have successfully embedded semi- conductors in a broad range of products. A con- sortium of industry and Academia in Europe, for example, developed and refined what they call the "die first" assembly method. The pro- cess begins with first embedding then inter- connecting the semiconductor die elements, a variation of the Occam Process extensively promoted by Joseph Fjelstad, the distinguished innovator. As described by the developers, the process begins with laser marking fiducial targets on the surface of an ultra-thin copper foil that serves as a base layer. A pattern of adhesive material that is slightly larger than the semi- conductor outline is then printed onto the copper surface and partially cured to furnish a stable tacky surface for device attachment. Using the fiducial target features on the copper surface as a guide, the component(s) is(are) placed into the partially cured adhesive pat- tern with the copper-plated terminal features of the die facing down. A thermal curing process follows to complete the bonding of the semiconductor element to the copper foil base. Resin-coated copper (RCC) foil is next laminated over the backside of die, encapsulating the element, followed by a microvia ablation and plating procedure sim- ilar to that outlined previously. Additional cir- cuit layers are sequentially added to complete interconnects to components mounted on the outer surface(s) of the substrate or printed cir- cuit board or package substrate. Outsourcing Embedded Semiconductor Processing In addition to processing the circuit board or package substrate, the designated PCB fabri- cator must be prepared to perform precise die attachment, have process capability for imple- menting a wide range of interconnect meth- ods, and provide full functional electrical test of the embedded semiconductors at the sub- strate level. Key issues to be addressed include: • Procurement of semiconductors in a wafer format • Outsourcing wafers for process-compatible metallization and thinning • Singulation process capability and bare die handling systems • Precise die placement and in-process termination capability • Electrical testing of the active embedded semiconductor Three questions that will need clarification are: • How should you test? • What should you test? • What features are needed to enable testing? Ideally, the originating companies will bring together the two primary suppliers: the circuit board fabrication specialist and the assembly service provider. SMT007 Vern Solberg is a technical consul- tant specializing in SMT and micro- electronics design and manufactur- ing technology. He has served the electronics industry for more than 35 years in areas related to both commercial and aerospace electronic product develop- ment and is active as an author and educator, focus- ing on technical issues related to PCB and flexible circuit design with an emphasis on electronic manufacturing using surface mount and related microelectronic components. Read past columns or contact Solberg.