Issue link: https://iconnect007.uberflip.com/i/1212069
REAL TIME WITH... IPC APEX EXPO 2020 SHOW & TELL MAGAZINE I I-CONNECT007 33 Now, SEMI wants to extend the standards down the supply chain to include assembly and box-build. A-SAP Averatek introduced a nanotechnology for palladium catalyst that allows the creation of fine-grained, thin electroless copper depos- its capable of being imaged and fabricated to 15-micron lines and spaces. Through Aver- atek's booth, technical papers, and a "commu- nity of interest" session, hosted by Tara Dunn, the company introduced A-SAP to IPC APEX EXPO attendees. You can expect: • Line width/space down to 15 μm/15 μm • 10X area reduction on the board • 90% reduction in space/weight over current state-of-the-art technology • Additional electronic functionality within an existing footprint • Licensed to leading domestic PCB fabricators for multiple suppliers VeCS I had a chance to talk with Joe Dickson, VP of R&D for WUS, about the roll-out and devel- opment of the vertical conductive structures (VeCS) construction developed by Joan Torné, NextGIn Technology BV. The reliability of this novel new process competes with HDI but uses all conventional multilayer fabrication equip- ment and processes (no laser drilling). See the sample Joe gave in Figures 1 and 2. Figure 1: (A) SMT side 0.75-mm pitch VeCS reliability daisy chain and (B) channel side of the 0.75-mm daisy chain. (Source: WUS PCB, Taiwan) Figure 2: Daisy chain examples (0.4, 0.65, 0.65, 0.80, 0.80, and 1.0 mm).(Source: WUS PCB, Taiwan) A B