Issue link: https://iconnect007.uberflip.com/i/1288481
100 PCB007 MAGAZINE I SEPTEMBER 2020 chemistry, and process control all affected the copper deposit structure. Magera recommended further FIB, SEM, and X-ray diffraction studies of microvia tar- get pads (as laser-drilled, before catalyst pre- dip and after electroless copper, correlated against process control data to identify criti- cal control variables) to determine the condi- tions required to produce consistent interface structures and identify the appropriate copper crystal lattice structure for best practice. And it was proposed that IPC-6012E 3.2.6.1 be updat- ed to better define the requirements for elec- troless copper. Day 1 Q&A John Perry then read questions sent in by at- tendees, followed by an open session for the speaker panel, with questions like, "What is needed to achieve and ensure reliable micro- via structures?" The ensuing discussion was lively and interesting. Many topics were dis- cussed, and the panel went 30 minutes longer than scheduled. Day 2 Chris Mahanna Day 2 opened with a presentation by Chris Ma- hanna—president, owner, and technical manager at Robisan Laboratory Inc.— titled, "We Experienced a Microvia Failure; Now, What Do We Do?" Chris opened with the statement, "With all the publicity around weak microvia interfac- es and the horrible functional failures caused by them, it is easy to become overwhelmed by their notoriety and the complexity of the prob- lem. Effective action needs to be taken to un- derstand and mitigate risk, but where does one start?" His presentation provided a framework for the failure analysis, variables to the related risk, corrective actions, and quality assurance to limit and quantify the risk. The three start- ing steps are: 1. Verify: Confirm that you have a weak in- terface microvia failure and not a simpler fail- ure. Isolate the failure to specific microvias. 2. Assess: Keep it simple by concentrating on three variables: (1) the density of your mi- crovias; (2) the Tg of your laminate; (3) and the susceptibility of your circuits to a marginal increase in propagation delays through the in- terconnects. 3. Take action: Take steps to dramatically re- duce future risks by changing the design. Con- sider your fabricator's capabilities and/or in- stall screening immediately. Lance Auer Lance Auer, an Engineering Fellow at Con- ductor Analysis Technologies, discussed "Per- formance-Based Microvia Reliability Testing: What You Need to Know." Auer discussed the implementation of a performance-based reli- ability test methodology: • Test sample (coupon) must match production board, holes and lands, staggers, spacing, fill, signal/plane layers, and solder mask • Convection reflow assembly simulation per IPC TM-650 2.6.27B • Air-to-air thermal shock per IPC TM-650 2.6.7.2C Both test methods are examined in detail with respect to the requirements of the test system: • Control and performance • Data acquisition • Documentation and reporting Auer summarized the recommendations for performance-based acceptance testing, which was agreed at the IPC APEX EXPO 2020 com- mittee meetings must represent the boards be- ing manufactured and the time/surface tem- perature of reflow. He demonstrated the ther- mal profiles for reflow simulation and ther- mal shock testing and showed examples of change-in-resistance measurements corre-