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OCTOBER 2020 I SMT007 MAGAZINE 21 Wesling: It involves the chiplets and higher lev- els that are up and down the stack (Figure 1). Johnson: Since our readers are primarily attuned to PCB manufacturing, how is the technology in the HIR going to change what happens on the PCB? Wesling: First, I want to address co-design and simulation. We expect that instead of finding local maximums or optimization for IC layout and then having to have a lower level of optimization at the board level and system level, we hope to trade off across the whole stack of technology. We expect PCB people to be working backward with the IC and chiplet design. It will be a challenge for CAD/EDA companies to provide the tools. Andy Shaughnessy: That's a fun- damental change in how you do your job, who you communicate with, and what you commu- nicate to them. Happy Holden: We can't depend on Moore's Law any more. With five to seven nanome- ters for gate geometry, we're not getting all of our future gains by going to one nanometer, 0.1 nanometers, and 0.001 nanometers. The alternative would be putting multiple chips together in a different material, in some fashion, to make these future gains in perfor- mance and lower cost. It's not going to just be the single chip with all the horsepower of that single chip. Wesling: We expect single chips to keep pick- ing up more parts of the system, but the ther- mal and design and interconnect limitations aren't going to make that possible—except for special cases, high volume, or something like IoT. We expect to see better optimization. The board-level people must have models that can be extracted and pushed down to the chiplet level and the interconnects and the wafer-level processing stuff. There may be better models needed at the PCB level. Testing is likely to change a lot. We hope to have a lot of known good die since it will be dif- ficult getting access to things without having to scan in or scan out for all the parts at the board or the system level. There's going to be a testing issue, which is covered a lot in the test chapter. It may prove difficult for the board-level people to move to new materials, different intercon- nect speeds, different intra-process testing, etc. Dan Feinberg: You mentioned chiplets quite a bit, which is relatively new. When do you recall chiplets first becoming commercially avail- able in relevant places? Wesling: Two years ago, I remember the DARPA thrust on chiplets. We would call them individual chips or subsets. Our roadmap cov- ers both. We've adopted the idea that you have a bunch of chips and a bunch of passives, such as inductors and capacitors, and then make your system with interconnects. Feinberg: Advanced Micro Devices (AMD) was the one that made great use out of it. They went from a lap behind Intel to a totally dif- ferent racetrack because of chiplets. There are a lot of other uses for it, but what would you think is the driver? For me, the driver of chiplets has been the move toward 50- and 100-thread CPUs. Wesling: Lisa Su, AMD's CEO and president, highlights that. It was their earlier generation, which we cover in the roadmap, that split that big chip into four chiplets to spread the power to make interconnect better and hook it up to memory better. That was an excellent applica- tion and probably the first major one we saw. Aerospace and defense think chiplets will be their salvation for building systems because they can't build SOCs; they may only build 200 of their design. They need to use commercial chiplets and make their systems using your inter- Figure 1: Intel Agilex FPGA Chiplet application. (Source: Intel)