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62 PCB007 MAGAZINE I OCTOBER 2020 To promote chemical bonding to the resin surface, Systek SAP includes a conditioning step after desmear that adds functional groups to the resin surface, followed by a convention- al cationic conditioner. The next step activates the surface with ionic palladium activator and reducer baths. The electroless copper seed lay- er plating can be done with Systek SAP Copper 850, an optimized formulation for near-zero in- ternal stress with tensile strength up to 30,000 psi and elongation between 10–14%. Throwing power of the electroless copper in an SAP process needs to be excellent so that a uniform coating is plated across the entirety of the microvia structure. Figure 5 shows the via structure after Systek SAP with Systek Cop- per 850, the copper thickness on the substrate surface and at the via target pad, and the sub- sequent filling after electroplating with Systek UVF 100. Peel strength measurements are taken by plating a minimum of 30 µm of electrolytic copper and then peeling the foil from the di- electric surface with an Instron Universal Test- ing System. Peel strengths exceed the custom- er's target on the three buildup films tested. A leading-edge advanced SAP for 1–2-µm line/space has been developed for R&D feasi- bility projects at this time. This advanced met- allization uses a non-formaldehyde electroless copper and electrolytic flash for minimization of undercut after the final etch. Electrolytic Copper Plating for RDL The most common type of electroplated structure for package routing in IC substrates is the redistribution layer (RDL), which creates horizontal and vertical axis interconnects for relocating I/O pads of the integrated circuit. RDL is used to create connections within het- Figure 4: Below-spec roughness of substrate material is a desirable property for substrate electrical performance. Figure 5: A uniform coating during the SAP seed layer plating is necessary for reliable via filling.