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64 PCB007 MAGAZINE I OCTOBER 2020 adsorbing on the copper surface through inter- action with the chloride ion. The leveler sup- presses plating rate by increasing the diffusion layer thickness. Through the effect of their combined mech- anisms, these chemical additives alter the electrical properties at multiple locations on the cathode surface as the via bottom-up fills, resulting in a leveling off of plating once the surface has become uniform. This is known as curvature-enhanced-accelerator- coverage (Figure 8). Copper via fill additives are optimized for different plating methods. In any-layer plating, the carrier is formulated for high suppression of the surface copper. The plating process is done by panel plating, so there is little varia- tion of the surface current density. Vias can be filled with as little as 10 µm of surface copper thickness. This is advantageous for use with ultra-thin mSAP foils and tent-and-etching in the advanced tenting process. RDL via fill additives are optimized for pat- tern plating. The design of the carrier molecule is to promote straight wall pattern plating with a minimum of doming. RDL plating is designed to plate the conductor height uniformly regard- less whether the structure is a fine line or land area. The panel shown in Figure 9 was pattern plated with Systek UVF-100 and featured 128 pieces (32 mm x 45 mm units) with vias 60 µm wide x 30 µm deep and 18/25 µm line/space, plated at 1.94 ASD (18 ASF) for 50 minutes in a VCP plating tool. RDL plating baths are versatile tools for the IC substrate fabricator. The process is most typically run in a vertical continuous plater (VCP) with direct impingement by mini educ- Figure 8: Curvature-enhanced-accelerator-coverage is the result of interactions of the wetter, brightener, and leveler over the course of bottom-up via filling. Figure 9: Systek UVF 100 pattern plating on IC substrate RDL.