Issue link: https://iconnect007.uberflip.com/i/1305670
64 SMT007 MAGAZINE I NOVEMBER 2020 Figure 4: PCQR 2 artwork available, 14-layer via rigid board illustrated by cross-section showing thickness ranges and various through-hole, blind, buried, sub-composite, and back-drilled vias (pcbquality.com) [3] . (Figure 5—c, d, and e). These are available for free from the coupon generator software at hats-tester.com. Many companies are purchas- ing the unit due to the speed and efficiency of this system. Interconnect Stress Test The IST is the oldest and most used acceler- ated thermal via reliability system in the indus- try. Developed in 1989 by Digital Equipment of Canada, patented in 1994, and commercial- ized by PWB Interconnect Solutions in 1995, over 120 systems have been installed world- wide. Used by over 120 OEMs, EMSs, and PCB fabricators, it has six licensed service centers around the world and is standardized by the IPC-TM-650 Test Method 2.6.26, the DC cur- rent induced thermal cycling test. A typical coupon is shown in Figure 6a. This is one that the OEM supplies for an IPC Class 3 board. This one has through-holes, blind microvias, and buried vias using a high-Tg, low-loss laminate. Two of these coupons are built with every board, and until an approved number of IST cycles are passed, it is not assembled. Failure means a return to the fab- ricator for analysis. The IST method measures changes in resis- tance of vias and internal layer connections as the holes are subjected to thermal cycling. The thermal cycling is produced by the appli- cation of a high current through the resistive