Issue link: https://iconnect007.uberflip.com/i/1309864
40 PCB007 MAGAZINE I NOVEMBER 2020 that need multiple chips on PCIE and mez- zanine cards, which they can't do even with HDI and through-hole; there are physical lim- itations as to why they can't do it. VeCS can enable them to put more than two chips on a single card. That's huge because the signal links can be reduced by half, and they're able to keep speeds for which they otherwise would need to switch to optical. But instead, they can stay in copper. That's where I see the advantage of VeCS for the network. For the AI and automotive side, we can do much larger BGAs then either HDI or through-hole really are capable of doing today, and I see that application being there. I see this technology becoming much more mainstream and a tool in the toolbox where it's no differ- ent. You use VeCS in one location, use HDI in another location, and through-hole in another, or you can use HDI on top of a subpanel VeCS with much fewer layers. Tourné: The next five years for me is just bring- ing the technology to volume production, even if it's in the simplest form. That's the first step. We're working on that now in some real de- signs and bringing that live, even with refer- ence designs. A lot of work is done with chip manufacturers and OEMs. Five years from now, I want to do just like we did with lasers. Lasers were very slow at the time, and they're much faster now. Hav- ing a slot forming process that's much fast- er, we want to apply for cellphone-type ap- plications where we can do 0.4-, 0.3-milli- meter pitch packages. That's key, and there's even the technology arising that we want to use for backplanes and press-fit applications. It's a completely different angle altogether, but there's a lot of interest in that as well. Matties: What's the trigger point for somebody to say, "Now is the time for us to use this tech- nology"? Is it reliability, functionality, etc.? Tourné: If you look at a lot of designs out there, it's a lot of HDI. It's five and six laminations or even higher. If they can bring it back to one or two laminations, that would be a big cost re- duction. Even if the SI performance is slightly better with VeCS; the main driver is cost. Johnson: That dramatically simplifies your de- sign and increases reliability. Dickson: What we've found is that with a lot of the collaboration, the chip manufacturers deal with us on the reference design test vehicles and the SI demonstrators. However, they talk mostly with Joan on the next-generation structures and where things are going from the chip through the substrate through the PCB back to the next chip. We're talking a lot more now to OEMs. Three years ago, we talked to the OEMs and introduced the technology. There was a lot of momentum from them, but there was confu- sion on how to move to the next level. Strate- gically, the focus changed to the chip manu- facturers, and pretty much all of them are now somewhere on the maturity level of moving to a reference design. They've done the steps to take that. VeCS-2 applications will challenge HDI the most. With channels (slots) formed from both sides, the 3D vertical traces provide greatly increased density without sequential laminations. Replacing larger through-hole vias with slots provides better PI for new power-hungry chips while lowering inductance and capacitance for improved SI.