Issue link: https://iconnect007.uberflip.com/i/1313710
DECEMBER 2020 I SMT007 MAGAZINE 69 future space projects (2020-2025). Feedback from the PCB/SMT WG members and other stakeholders was requested to specify the tech- nological need while keeping in mind the pos- sible repercussions on manufacturability and reliability. Starting from the functional require- ments and component needs for future space projects, a set of advanced technology parame- ters is derived for evaluation within the project. During the workshop, it became clear that the split into technology for near-term and future projects was not satisfactory as higher complexity was required in the near-term as well. The decision was made to differenti- ate between basic HDI technology, intended for qualification within the project, and com- plex HDI technology, including more advanced technology parameters. The workshop con- firmed the large FPGA components—based on 1.0-mm pitch CCGA packages with up to 1752 pins—as primary drivers for the basic HDI tech- nology. In addition, AADs with 0.8-mm pitch and a few hundred I/Os should be compati- ble with the basic HDI technology. Other driv- ing components are small passives (0402 chip components), and fine-pitch lead frame com- ponents (QFP 0.5 mm) when routing space is limited. In future projects, components will have up to 2000 to 3000 I/Os and will use AADs with 0.8- and 1.0-mm pitch. These will likely be non-hermetic polymer-based pack- ages (PBGA), as a package size of 45 mm x 45 mm for ceramic packages is the limit in terms of CTE mismatch. A further reduction in pitch to 0.5-mm pitch is expected for low I/O (200– 300) and for memory devices. The HDI technology parameters for basic and complex HDI, as agreed during the work- shop, can be found in Table 1. The basic HDI technology consists of a single-sequence core Table 1: HDI technology parameters for basic and complex HDI technology.