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22 DESIGN007 MAGAZINE I FEBRUARY 2021 Semiconductor packaging has traditionally utilized a narrow strip of organic copper-clad organic-based laminate and wire-bond pro- cessing for the single-die BGA. Companies furnishing devices for high-volume markets are now implementing very fine-pitch alloy bumped flip-chip package technologies that enable face-down interface. e terminal size and pitch are oen, however, far too small for conventional organic circuit board fabrication capability. To better accommodate die-to- substrate interface, several companies are suc- cessfully adopting wafer-level and panel-level package technologies. Wafer Level Packaging Silicon materials are commonly furnished in a 200-300 mm diameter wafer format sized to be compliant with the existing semiconductor fab- Developing Panel Level Semiconductor Packaging rication infrastructure. Most commercial semi- conductor manufacturers utilize these thin sili- con wafers to provide a stable base for integrated circuit processing, but the silicon-based mate- rial has also proven to be an excellent choice for wafer-level packaging because it perfectly matches the CTE of the silicon die element(s) that will be mounted onto its surface. Fabrication of the fan-out or fan-in/fan-out interposer is commonly performed within the semiconductor foundry environment. Die elements are arranged on the wafer's surface in a row and column format, with the active surface facing up for wire-bond interconnect or face-down when furnished with alloy bump terminals. e processes for via-hole ablation and metallization in the silicon material are very different from the basic semiconductor man- Designers Notebook by Vern Solberg, CONSULTANT