Issue link: https://iconnect007.uberflip.com/i/1337116
86 DESIGN007 MAGAZINE I FEBRUARY 2021 bedrock, and finally the BOM served to pro- vide quick reference. When CAD became sta- ble and made it easier to integrate the "hard math" of the EE to a reasonable degree, the math began getting kicked to the curb. Today, fewer and fewer designers have the "scar tis- sue" of the earlier veterans and thus have the ability to fully appreciate the fundamental importance of planning. e 80% rule was not optimum but satis- factory for the early SMT industry. Where it missed opportunity was when it was applied to area array packages such as BGAs and CSPs. Area array land patterns have an intrinsic advan- tage: If all devices conform to the use of a com- mon base grid such as 0.5 mm or 0.1 mm, trace, via, and plane artwork creation is streamlined because the component count options drop dramatically and layer counts can be signifi- cantly reduced. e lesson is this: When lead pitches are fewer in number, vias fall on larger grids, and the routing lanes (trace + gap) align, thus creating less "hypotenuse diagonal" trace length across the circuit layout. is is graphically illustrated in a design comparison done by PCB design master Dar- ren Smith of Athena Tech and published in Solderless Assembly For Electronics: e SAFE Approach, available for free download in the I-Connect007 eBook library. e sage CEO of a consulting company I worked for in the late 1990s was oen heard to say, "Too soon old, too late smart," when seeing that simple solutions were oen over- looked or unrecognized in our problem-solv- ing efforts. However, I have attached to that thought another time-worn aphorism: "Bet- ter late than never." We are learning beings if we allow ourselves permission to do so and think beyond the pale. As Mark Twain said, "It's not what you don't know that gets you into trouble; it's what you know for sure that just ain't so." So, I believe the fundamental answer to the question posed in the title of this column is that there are far too many options. JEDEC allows virtually any package outline and pitch configuration to be registered and we are overloaded with options. I personally believe that fewer options, especially when all com- ponents share a common lead pitch for IC package terminations (my suggestion is 0.5 mm, the pitch below which soldering becomes progressively more difficult) is both simpler and better for design and manufacturing. However, one of the strange ironies of achiev- ing simplicity is that it generally takes more forethought and discipline to execute a simple design than it does for more complex ones. So it goes. FLEX007 Note: anks are extended to design expert Darren Smith for his reviewing skills and valu- able comments. Joe Fjelstad is founder and CEO of Verdant Electronics and an international authority and innovator in the field of electronic interconnection and packaging technologies with more than 185 patents issued or pending. To read past columns or contact Fjelstad, click here. Download your free copy of Fjelstad's book Flexible Circuit Technology, 4 th Edition, and watch his in-depth workshop series "Flexible Circuit Technology." Today, fewer and fewer designers have the "scar tissue" of the earlier veterans and thus have the ability to fully appreciate the fundamental importance of planning.