Design007 Magazine


Issue link:

Contents of this Issue


Page 19 of 121

20 DESIGN007 MAGAZINE I JULY 2021 Rick Hartley: When connecting bypass/decou- pling capacitors to power/ground planes, each capacitor should be connected with its own set of vias. Sharing vias between caps should be avoided unless absolutely necessary (in cases where component density is extremely high). e best connection arrangement is the one with the lowest via pair inductance. Low via pair inductance is achieved when the power and the ground vias are very close together and very near the capacitor pins. Large vias that are far apart have higher inductance than small vias that are close together. Close spacing, not large size, is the key to low via inductance. Using multiple values of bypass/decoupling capacitors is generally not a great idea. Doing so can, and oen does, lead to problems with anti-resonant peaks in the power bus imped- ance, caused by the parallel resonance of the capacitance of one device relative to the induc- tance of another device of a different value. Multiple values can be implemented success- fully, but will require extensive simulation with a high-end power bus simulator, to minimize anti-resonant peaks. High power bus imped- ance at any frequency can cause SI and EMI issues. Heidi Barnes: First, capacitors should be selected for flat matched impedance and not just "factor of 10" old-school leveraging. If a large cap is placed next to a small cap one can have a Pi resonator between the ESL of the large cap and the C of the small cap. Selecting the right ESR to achieve a target Z will help reduce the number of caps by maximizing the bandwidth of power delivery for each capacitor before the next capacitor takes over. Next, as your ques- tion asks, is the importance of ground and power vias to have low inductance to the com- ponent power pin. e best way to do this is to start with a thin dielectric between the power and ground planes to form a parallel plate with small loop inductance. ree mils is typically sufficient and can significantly reduce both the via loop inductance as well as the path induc- tance to the load. Finally, using capacitor foot- print topology that gets the power and ground return vias as close as possible will help reduce the inductance further. To maximize the high frequency bandwidth, the smallest capacitor should be placed as close as possible to the power pin. In the case of BGA devices this is typically on the opposite side of the part directly across the power and ground vias to the BGA. Eric Bogatin: Why use different value capaci- tors on the same power pin? As a general rule, never share power or return vias. What is the best method for tying vias to ground and power planes for bypass capacitors when using multiple caps of different values for one component power pin? Q

Articles in this issue

Archives of this issue

view archives of Design007 Magazine - Design007-July2021