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34 DESIGN007 MAGAZINE I JULY 2021 Rick Hartley: Crosstalk is getting worse, due to the many ICs of today with very fast rise and fall time outputs. Crosstalk, like many prob- lems, is not related to clock frequency, rather to the rate of change of energy in transmission lines, due to most of today's ICs having rise times faster than 1 nsec, with some even faster than 500 psec. It only takes an inch of paral- lelism between two transmission lines to cause maximum crosstalk coupling between the lines when signals have 500 psec edges. ere are several techniques that can vastly reduce crosstalk: 1. Always route signal lines directly above a plane, preferably a ground plane. 2. Try to space critical lines (ones with really fast edges) at least 1X the distance to the nearest plane for inner layer routes, and 2X distance to the plane on outer layers. 3. Whenever possible, series terminate transmission lines that are fast enough to be an aggressor. Series termination vastly improves crosstalk, as well as ground bounce, EMI, power bus switching noise and ringing (vswr/return loss). 4. Only use "guard traces" when they can be attached to a ground plane with vias spaced every one-tenth wavelength of the highest frequency (0.5/rise time). Do not overdo this. Vias closer than one-tenth wavelength simply take up space and make routing on other layers harder. When signal traces can be spaced far enough apart to allow for a guard trace that is properly attached to a ground plane, you can likely eliminate the guard trace, since the aggressor and victim lines will be very far apart, typically six to eight times the distance to the nearest plane. To ensure that the above concepts have achieved the intended goals, use a 3D field solver or other high-end simulator to esti- mate crosstalk prior to building the board. e techniques mentioned here will not eliminate crosstalk, rather will reduce it to more accept- able levels. Carl Schattke: It's hard to know exactly what this question is asking and commenting on, but in general, smaller geometries in silicon are shrinking spaces and isolating circuits at the silicon level. is can reduce the noise margin at the PCB level and create problems as sili- con processing can make a previously working PC board nonfunctional as the silicon shrinks and takes more of that overall margin away. Re-designs will cost money, but sometimes that's your only option. Hopefully, the rede- sign can save money in other ways. Crosstalk is getting worse, after we had it under control. It's not just transmission lines anymore. It's almost laughable, but it's costing us money. What can be done? Q

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