Issue link: https://iconnect007.uberflip.com/i/1391285
84 DESIGN007 MAGAZINE I JULY 2021 To systematically design a PDN filter, first we must establish the requirements. In PDN design work, the biggest pain for a board designer is that input requirements that would guide the designs are very rare, many times almost non-existent. Establishing PDN requirements is oen le to the PDN and board designer. ere is one situation, though, when the board designer should be in the position to establish the filter requirements properly: when we need to attenuate the output ripple of a switching regulator for a sensitive pin of a chip that has a specified maximum allowed noise. To quote some simple numbers, the typical peak-to- peak regulator ripple may be around 10 mVpp, which is usually too much for a sensitive analog circuit, such as a reference clock or clock buffer circuit, PLL, SerDes supply, or sensitive analog circuit, more likely requiring around 1 mVpp maximum noise. In such cases, relying on the allowed ripple voltage limit of our sensitive cir- cuit and having an estimate of the regulator's switching frequency and output ripple, we can determine an attenuation requirement, at least at the switching frequency of the regulator. As an illustration, let's take a filter circuit that is supposed to attenuate 10 times the switch- ing ripple of a DC-DC converter running at 500 kHz for an oscillator circuit that takes just a few milliamperes of current. In addition to the series inductive element and the output capac- itor, the circuit in Figure 2 also includes com- ponents that model the source side of the fil- ter. R1 and L1 represent the impedance of the DC source, and C2 and C3 with their parasitics model the board capacitors. e L5-R5 circuit is the model for a small inductor. As opposed to a ferrite bead, where we would anticipate a large increase of series resistance and a sub- stantial drop of inductance at high frequencies, this simple inductor model has frequency- independent series resistance and inductance. e filter output is a single capacitor, mod- eled by C4-R4-L4. Note that this model inten- tionally has a very high ESR for C4 that we can get either from a small electrolytic capacitor (though it will likely have a much higher ESL) or we can use a regular ceramic capacitor with low ESR and add a 0.91-ohm series resistor. We also knowingly ignore the printed circuit board details and therefore we limit the AC simulation to below 100 MHz. e filter behav- ior at higher frequencies will be influenced and probably dominated by component place- ment, the PCB layout and stackup—something that is beyond the scope of this article. We simulate the filter circuit in the frequency domain in the 100 Hz to 100 MHz frequency Figure 2: Schematics of a simple one-stage PDN filter.