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AUGUST 2021 I DESIGN007 MAGAZINE 69 • Pay attention to routing. For example, you want your analog grounds crossed only by analog lines. is will reduce capacitive coupling on a large ground plane with lines routed above and under it. A Designer's Best Friends: Vigilance and Awareness Designing with voltage top of mind is vital, as is knowing what the design tool's error checker will and will not catch regarding connections to split planes. is is how you avoid burning boards and doing costly rework. If you build your designs such that you can rely on auto- mated error checking, we believe that is the best method for dealing with complex power plane schemes. DESIGN007 Matt Stevenson is the VP of sales and marketing at Sunstone Circuits. To read past columns or contact Stevenson, click here. Column Excerpt by Suketu Desai CADENCE Today's data-thirsty world is looking forward to the next-generation communication systems beyond 5G, the promise of massive connectivity to the inter- net with extreme capacity, coverage, reliability, and ultra-low latency, enabling a wide range of new ser- vices made possible through innovative and resilient technologies. The exponential growth in data speed and networking has introduced numerous design and analysis challenges across a system design. Design teams are challenged to deliver new, differ- entiated products faster and more efficiently, despite the ever-growing complexity of silicon, package, board, and software for many complex applications in the hyperscale computing, automotive, mobile, aerospace, and defense markets. Fragmentation Challenges Design flows are fragmented across chip, pack- age, board, and system levels, making end-to-end simulation harder. An accurate 3D model is the most accurate and reliable method to achieve structure optimization and high-speed compliance of the com- plex structures found in silicon interposers, rigid-flex PCBs, stacked-die IC packages, connectors, and cables. A high-fidelity interconnect design is a critical factor for high-speed signaling, such as 112G SerDes interfaces that are highly susceptible to any change in impedance that negatively impacts the bit error rate. Optimization entails extensive what-if analy- ses, including dozens of complex extractions and simulations. The alternative method using legacy tools requires users to partition a design, do piece- meal modeling and analyses, and stitch the results together. This method introduces accuracy loss, user errors, and risk. In addition, the need to merge mechanical structures such as cables and connec- tors with the system design to create one compre- hensive model and simulate as a single piece can- not be accomplished. Click here to read the rest of this column. Suketu Desai is senior director of product engineering, Multiphysics System Analysis Group, Cadence Design Systems, Inc. ALL SYSTEMS GO! Challenges in Analyzing Today's Hyperconnected Systems Figure 1: Real measurement from PAM4 silicon (left) compared with modeled output (right).