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80 PCB007 MAGAZINE I OCTOBER 2021 Extensive IST testing has revealed that VeCS coupons achieved 10 to 30 cycles while conventional PTH had a range of seven to 10 cycles (Figure 8b). Additional data is available from NextGln. Future Enhancements e current focus is on the use of HDI micro- vias to enable VeCS applications for fine pitches down to 0.15 mm. e micro-VeCS process is shown in Figure 9 for inner layers. VeCS/HDI will scale down the feature sizes for VeCS to enable it to run smaller devices pitches–device pitches down to 0.15mm are possible, as seen in Figure 10. e benefits of VeCS/HDI are: • No materials limitations. Use flat weave materials to support the laser processing • Compete with HDI constructions and take advantage of reduced lamination cycles reducing lead time and complexity • Single lamination process versus 5 or more laminations • Reduce cost by 40-60% • Higher yields Additional information is available at PCB007, EIPC Winter Conference, Linke- dIn 7,8,9 and by contacting NextGIn Technolo- gies. PCB007 Figure 9: The micro-VeCS process as follows: a) laser cutting the cavity; b) plating the cavity; c) apply positive electrodeposited resist; d) direct expose the resist; e) etch and strip; f) fill VeCS slot.

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