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22 DESIGN007 MAGAZINE I AUGUST 2022 ey're only necessary on high-density and high-frequency complex boards, so you should typically not need them. Microvias are rela- tively costly for simpler designs, but for more sophisticated PCBs and prototypes, they are the prime solution. ey also reduce layer count which is a cost-saving. Blind and buried vias are also used to reduce the board aspect ratio. e minimum via hole is determined by drill size as well as the aspect ratio, which is the thickness of the PCB divided by the diam- eter size of the drilled hole. ere is usually an additional manufacturing cost for aspect ratios higher than 8:1 for PTH and 0.8:1 for micro- vias. e efficiency and design freedom pro- vided by blind and buried microvias are some of the reasons why PTHs are rapidly becom- ing a thing of the past for complex designs, especially since most of the components that require PTHs to be mounted on a PCB are bulky and space-consuming, whereas dense BGA designs are more suited to the use of microvias. Cost is also relative to the trace/clearance requirements of the technology employed. e larger the trace/clearance, the less the cost. Going below 4/4 mil technology will incur a cost premium. e use of mixed signal/power planes can reduce the need for additional plane layers to keep the layer count down. Look for different design options to make sure your board is as simple as possible. Not only do you want to optimize the elements of the board, but you'll also want it on a small form factor that still provides appropriate clearance for every element. Material selection is another cost consider- ation. When each material is used for the right target application, the resultant PCB will have the lowest possible cost while still satisfying the design and performance goals of the proj- ect. In Figure 1, I have selected a 10 GHz Isola TerraGreen material with a Dk of 3.3 and a dissipation factor (Df ) of 0.003 for its low loss capabilities. Now, this may be necessary for our high-speed DDR4 signals but is not a Figure 1: Ten-layer high-speed PCB stackup. (Source: iCD Stackup Planner)