Issue link: https://iconnect007.uberflip.com/i/1478618
24 DESIGN007 MAGAZINE I SEPTEMBER 2022 Keep these tips in mind when planning the board stackup: • All signal layers should be adjacent to and closely coupled to an uninterrupted reference plane, which creates a clear return path and eliminates broadside crosstalk. • ere is good planar capacitance to reduce AC impedance at high frequencies. Closely coupled planes reduce AC impedance at the top end and dramatically reduce electromagnetic radiation. • High-speed signals should be routed between the planes to reduce radiation. • Reducing the dielectric height will result in a large reduction in your crosstalk without having a negative impact on available space on your board. • e substrate should accommodate several different technologies. For example, 50/100 ohm digital, 40/80 ohm DDR3/4 and 90 ohm USB. Unfortunately, not all these rules can be accommodated on a four- or six-layer board simply because we have to use a buffer core in the center to realize the total board thick- ness of 62 mils. However, as the layer count increases, these rules become more critical and should be adhered to. Given the luxury of more layers: • Electromagnetic compliance (EMC) can be improved or more routing layers can be added. • Power and ground planes can be closely coupled to add planar capacitance, which is essential for GHz plus design. • e power distribution networks (PDNs) can be improved by substituting embedded capacitance material (ECM) for the planes. • Multiple power planes/pours can be defined to accommodate the high number of supplies required by today's processors and FPGAs. • Multiple ground planes can be inserted to reduce the plane impedance and loop area. Although power planes can be used as ref- erence planes, the ground is more effective, as local stitching vias can be used for the return current transitions rather than stitching decou- pling capacitors, which add inductance. is keeps the loop area small and reduces radia- tion. As the stackup layer count increases, so does the number of possible combinations of the structure. But if one sticks to the basic rules then the best performing configurations are obvious. So, the big question everyone asks is about determining layer count. A good place to start is looking at a reference design with similar characteristics and then adding two layers. I say to add two additional layers because ref- erence designs are typically squeezed onto as few layers as possible. But if one wants to avoid routing signals on the outer microstrip layers and reduce signal propagation skew and elec- tromagnetic emissions, the extra layers will be needed. Experienced PCB designers get a feel for it aer a while, but a good way to check whether you have enough layers is to autoroute the board. With no tweaking, the autorouter needs to complete at least 85% of the routes to indicate the selected stackup is routable. e performance of the autorouter also impacts the completion rate. You may have to re-eval- uate the placement a couple of times to get the best results. In general, eight layers is a good starting point for DDR type designs. Remem- ber, it is much easier to increase the number of layers than to reduce them, so start with the minimum. A field solver can be used to determine the unknown variables for an established imped- ance goal (Figure 1). Impedance plots use multiple passes of the field solver to plot the curve of impedance vs. dielectric thickness. In this case, a 3-mil prepreg is required to achieve