Issue link: https://iconnect007.uberflip.com/i/1478618
26 DESIGN007 MAGAZINE I SEPTEMBER 2022 in the stackup close to and directly below/ above the IC. is reduces the loop inductance dramatically (Figure 3). e ability to extract the plane data and via definition from the stackup to a power distribu- tion network (PDN) planner is also an advan- tage as it allows one to see the plane resonance and the impact it has on the AC impedance of the PDN (Figure 3). e AC impedance of the PDN should be kept below the target imped- ance up to the fih harmonics of the funda- mental. Plane resonance can be dampened fur- ther by adjustments to the dielectric constant and thickness as well as plane size to avoid anti-resonance peaks. Setting up the via span is also important at the stackup level (Figure 4). is gives you a clear defi- nition of all the plated through-hole and blind and buried vias used in the design, and can be con- veyed to the fabricator. If one has no choice but to route critical signals on the outer microstrip layers then there will be a large discrepancy in timing due to the variance in flight time through different materials of the outer microstrip and inner stripline layers. Figure 3: Plane pair data and via size is extracted from the stackup to the PDN (iCD Design Integrity). Figure 4: Via span definition is defined in the stackup (Source: iCD Stackup Planner).