Issue link: https://iconnect007.uberflip.com/i/1507356
38 DESIGN007 MAGAZINE I SEPTEMBER 2023 Return Path Vias Challenge On the le side of Figure 5, the green lines are data line (DQ) signal vias and the pink area is the ground (GND) via, which is stitching two ground planes together. On the right, one of these signals has a trace on the green top layer and the second line is going to be the reference with an ideal return path. However, the return current must traverse to the second-to-last layer, and it does so by find- ing the closest path possible. While the signal goes directly to the signal via, the return path is right underneath the signal and then must find its way to the stitching via and come back so it is referencing on the bottom layer again. e same thing is happening for all the signal vias—they are all using the same stitching via as the return path, which causes via-via cross- talk. is is a 3D phenomenon, not a simple 2D side-by-side problem. A 2.5D or 3D analysis is needed to accurately model this, and while it is traditionally the SI expert's wheelhouse, Sig- rity Aurora analysis workflows enable the non- SI expert to do this. JEDEC Specification Complexity e JEDEC specification is incredibly com- plex and confusing with an "alphabet soup" of requirements. (V ix , t DQSS , t DSS , t DS , t DSH t DH , t VAC , etc.) and the requirements vary by technol- ogy such as DDR, low-power DDR (LPDDR), graphics DDR (GDDR), by version (DDR3 versus DDR4), and by bus, such as address vs. data vs. clock signal (CLK) vs. DQ strobe (DQS). For example, DDR4 data has a rectan- gular eye mask requirement, which needs bit error rate (BER) measurements, but for DDR5 that measurement is now a diamond shape. For the PCB designer, this can be a daunting challenge, but analysis workflows from the Cadence PCB layout environment allow access to the Sigrity PowerSI and Clarity 3D Solver extraction engines to support detailed and accurate modeling of interconnect as part of a simple, easy-to-use solution for SSN, return path via, and JEDEC specification challenges. Interconnect Model Extraction At the later stage of the DDR workflow, the nets have been laid out and preliminary DDR checks have been completed. Now 2.5D or 3D interconnect model extraction is required for layout verification. is can be done on a sec- tion, a channel, or a handful of signals, depend- ing on how much time is available. Based on what has been extracted, a quick waveform val- idation can be performed to make sure that the waveforms are correct (Figure 6), or a quick DDR analysis can be run using the PowerSI 2.5D or Clarity 3D Solver to ensure the design meets all the requirements. is enables the designer to also observe via- via crosstalk effects, power-aware effects, and other advanced effects, and slowly and steadily Figure 5: Return path for signal vias.