Issue link: https://iconnect007.uberflip.com/i/1507356
36 DESIGN007 MAGAZINE I SEPTEMBER 2023 several or all the lanes (depending on how much time is available), and running either a 2.5D or full 3D analysis on the entire channel (Figure 2). Using the results of the channel extraction, a compliance analysis can be run based on the desired protocol. Most likely this will not be a one-time event, as oen some obscure requirement not identified in the preliminary phase will surface, requiring additional itera- tions. DDR Compliance Analysis Flow DDR, while not as fast as SerDes, and in some ways not as sophisticated, can present more challenges for signal integrity (SI). Some DDR speeds can overlap with the lower end of the SerDes spectrum and there are many nets, both single-ended and differential, that have complex SI requirements. DDR Design Challenges Early-stage DDR SI issues typically involve general problems like impedance matching and discontinuities, stubs like dual in-line memory modules (DIMMs), termination opti- mization, and trace crosstalk. While these are basic requirements, it is important to consider them as well as the more sophisticated prob- lems, and the earlier the better. ese issues can quickly be examined by running sweeps with the Topology Explorer, such as what has been discussed with SerDes. e constraints can be determined through simulation sweeps, and those constraints can be saved with the schematics (Figure 3). Once the preliminary schematics with con- straints are generated, the layout phase begins. is is where IDA empowers PCB designers with early layout verification to provide confi- dence that the layout is correct and won't fail due to SI issues. is can be done by quickly running a host of general SI analyses (imped- ance, coupling, crosstalk, reflection, return path, etc.) in the Allegro layout environment with Sigrity Aurora workflows. ese analyses provide a visual representation on the trace of where the issues are, so rather than the typi- cal back-and-forth between the SI experts and layout designers to identify and correct the problems, the design can remain with the layout designer who can visually see the prob- lems and correct them right then and there. is shortens the design process. If the layout designer is unable to fix the problem, the topology explorer can be used Figure 2: Compliance workflow for accurately modeling the channels and addressing compliance specifications.