22 PCB007 MAGAZINE I SEPTEMBER 2023
2030 using 0.25/0.25 µm t/s. Figure 3 demon-
strates where the geometries of the two mar-
kets are superimposed as:
• Substrate vs. board
• Substrate vs. wafer level packaging (WLP)
• Organic WLP and dual Damascene
WLP vs. 2.5D IC packaging
• Ultra-HDI vs. wafer-level back-end-of-line
(BEOL) WLP
Conclusion
My prediction for UHDI is seen in Figure 3.
Conventional HDI are originally focused on
the introduction of small-blind vias of < 150 µm
(6 mil), and geometries in the 75 µm/75 µm
(3 mil/3 mil) trace/space. Ultra-HDI will have
even smaller microvias and t/s from 50 µm/
50 µm, (2/2 mil) down to ~5 µm/5 µm (0.2/0.2
mil)
4
. PCB007
References
1. Inspired by IEEE Heterogeneous Integration
Roadmap, Chapter 2, pp 10.
2. Happy's Tech Talk #5: Advanced Boards for
Heterogeneous Integration, PCB007 Magazine,
February 2022.
3. Happy's Tech Talk #4: Semi-additive Processes
and Heterogeneous Integration, PCB007 Maga-
zine, January 2022.
For more perspective on how UHDI is differ-
ent, read "A Primer on UDHI," by Anaya Vardya,
Design007 Magazine, September 2023, as well
as discussion on IC packaging and the CHIPS Act
(SMT007 Magazine, September 2023, and PCB007
Magazine, January 2023).
Happy Holden has worked in
printed circuit technology since
1970 with Hewlett-Packard,
NanYa Westwood, Merix, Foxconn,
and Gentex. He is currently a
contributing technical editor
with I-Connect007, and author of Automation and
Advanced Procedures in PCB Fabrication, and
24 Essential Skills for Engineers.
To contact
Holden or read past columns, click here.
Figure 3: The tradeoffs between dielectric thicknesses and trace/space (t/s) geometries for
heterogeneous integration are overlapping technologies of PCBs, IC substrates,
UHDI, WLP/PLP, and wafer interposers-BEOL
3
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