Issue link: https://iconnect007.uberflip.com/i/1507822
90 PCB007 MAGAZINE I SEPTEMBER 2023 and few perform any type of defect analysis to see why boards fail this test. HP's Sunny- vale Printed Circuit Facility (SPCF) set out to exploit the information potential of the board test process. Continuity testing occurs when a printed circuit is approximately 85% completed. Test- ing supplements PCB visual inspection, which was the only prior means for finding opens and shorts. e current average electrical defects at first test are reported in the HP PC Manu- facturing Standards, Section 407 (Raw Board Electrical Test). is section has details on HP's Electrical Test Standards. is includes when to test, test extent, electrical character- istics, and fixture documentation specification. e development of this standard has gone a long way in eliminating the uncertainty and unknowns with our (HP's) customers. e cri- teria of when to test a bare board is now a sim- ple equation. When to Test e debate on when, how much, and how oen to electrical test bare PCBs ended when Dr. W. Edwards Deming provided insight into the test and inspection question. In chap- ter 8 of his manual, "On the Management of Statistical Techniques for Quality and Pro- ductivity," he outlined the equations below. e essential elements in the decision are the average electrical defect, the cost to test one unloaded PC board, and the cost to test and repair it if a defected board is loaded. Esti- mates on the average defects are shown in Fig- ures 1 and 2. e following (provided by Dr. Deming to HP) are developed to minimize the average total cost of a lot. (1) e average cost of inspection of a lot of N parts is Y 1 , Y 1 = N ( P+Q x ) k 1 / q (2) e loss from ( N-n ) Q p defective parts that get into the production line is Y 2 , Y 2 = N ( 1-x ) Q p ( k 2 + k 1 /q ) (3) e average total cost per lot will be Y = Y 1 + Y 2 . Y = (N k 1 / q) [1+Q q ( kp-1) (1- x)] where K = ( 3). Figure 1: Electrical yield loss due to PCB complexity.