Issue link: https://iconnect007.uberflip.com/i/1507822
SEPTEMBER 2023 I PCB007 MAGAZINE 95 From the above, we can see that customer testing implies that the PCB manufacturer can only implement process feedback in a fashion that is too late with dubious data in an inconve- nient format (i.e., old error printout). Progress begins when a test system is brought in-house. In-house Testing to Raise Yield and Productivity It will be helpful to think of process feed- back as a constant endeavor to tune up and fine tune upstream processes and tools by learning from your mistakes. Yield improves when you quit making the same mistakes. Productivity improves in relation to yield. e key to effective feedback is information; the fact that an electrical test (ET) operation rejects more boards than any other process is simply an indication of this information poten- tial. e development efforts at SPCF toward exploiting ET information began due to needs in the ET area itself. Getting Started Now the testing happens in-house. Visual inspection is no longer a bottleneck, custom- ers are happy, and the test and troubleshooting areas are complementing each other. However, how do you use ET information to find why the bad boards failed, when you already seem to spend too much time finding a good board? Bare board test systems operate by compar- ing the electrical connections of a board being tested, with a memory representation of the connections in a "good board." Finding this ide- alistic "good board" can be a problem, especially for complex PCBs that will eventually show a 30% or higher failure rate. e amount of time spent in the "find a good board" mode directly depends on how oen new part numbers and revisions are tested, the complexity (and hence the yield) of these new boards, and the data reduction capabilities that are available. To give an example, we will assume that the self-learn mode of the test system is used to program the connections in a board sit- ting on the top of the stack to be tested. Next, the system is placed in the test mode and, say, 10 boards are tested, only to find that each of them shows an appalling number of errors. A perceiving question at this point is, "Just how oen are each of these errors occurring?" Error Correlation e concept of a communication link between a test system and an external or "host" computer has been a key to the developments at HP's SPCF. In response to the question of how oen each of these errors are occurring, SPCF developed a computer program that ran in a microcomputer which was interfaced to their first test system. When the test sys- tem detected an error in a board being tested, it would tell the microcomputer about it. e microcomputer would log it into memory, and on request, correlate all the logged errors and produce a display with the number of times each error was seen, from the most frequent on down. e program would also count the number of boards tested and failed, and pro- duce hard copy reports identifying the run, test results, and the most frequently correlat- ing errors. A sample report is shown in Figure 5. is relatively simple tool has the following major effects: 1. It differentiates between "systematic" and "random" errors. Systematic refers to the same type of defect occurring repeatedly in the same location. Systematic defects are the foundation of process feedback. 2. It provides a constant diagnostic on the test system and fixture. By doing a corre- lation occasionally while testing, intermit- tent pins are soon highlighted, and a quick check of the failed boards confirms this. 3. It allows a drastic time savings when finding a good board. For example, highly correlating opens at the top of the display point to probable shorts in the board that was programmed too.