Issue link: https://iconnect007.uberflip.com/i/1511130
NOVEMBER 2023 I DESIGN007 MAGAZINE 55 Figure 1: DDR3 synchronous timing. (Source: JEDEC Std 79-F3) Figure 2: Source synchronous timing relationship across substrate. natively, one can compensate for a delayed layer by adding delay intentionally using ser- pentines to the signal trace in question. Clocks are essential gatekeepers of the digital domain. Setting the pace for all that follows the clock can be a single trace or dif- ferential pairs that carry complementary sig- nals. Because each bit of the data bus must arrive and become stable before the clock cycle, the clock signals establish setup time for accepting or extracting the data. e hold time ensures that the entire bus remains steady during the read-in or read-out of data aer the clock. Fortunately, synchronous buses, as typically used for parallel data signal transfer, benefit from an extraordinary immunity to crosstalk. Crosstalk only occurs when the signals are being switched and this crosstalk only has an impact within a small window around the moment of the clocking. e crosstalk must be specified during the setup (t S ) and hold (t H ) window at the receiver. During this interval, the crosstalk must never drive any valid signal across the receive threshold to the opposite logic state. So, providing the receiver waits sufficiently long enough for the crosstalk to settle before sampling the data bus, the crosstalk has no impact on the signal quality at the receiver. If the crosstalk arrives during the signal transi- tions, then its only impact is jitter on the eye. However, this only applies to signals within the same group. Asynchronous and unrelated