Issue link: https://iconnect007.uberflip.com/i/1511130
58 DESIGN007 MAGAZINE I NOVEMBER 2023 If you are aware of this issue, then the trace delays (Figure 3) can be matched to compen- sate for the flight time variance, so that at the nominal temperature all signals running on either microstrip or stripline will arrive at the receiver simultaneously. It is good design prac- tice to route each memory bus on the same layers. at is, avoid routing on the surface layers other than fanout, and drop immedi- ately to the internal stripline layers routing all data, address, associated clocks/strobes, and control signals on the same layer pair to avoid propagation delay variance. Key Points • Electromagnetic energy propagates at about half the speed of light within the dielectric of a multilayer PCB. • e lower the Dk, the faster the propaga- tion of the wave. • Designing a memory interface is all about timing closure. • e signal and the timing, relative to other signals, ride on an electromagnetic carrier wave at various speeds, depending on the surrounding dielectric materials. • is energy transports the signal from the driver, along the transmission line to the load, and does not disrupt the original timing but rather adds the same delay to all the signals that travel the same path. • Clocks are essential gatekeepers of the digital domain. • Synchronous buses benefit from an extraordinary immunity to crosstalk. Crosstalk only occurs when the signals are being switched and this crosstalk only has an impact within a small window around the moment of the clocking. • Asynchronous and unrelated signals always remain sensitive to crosstalk. • From a PCB designer's perspective, we can only optimize what we can control and that is just the placement and routing. • Even if the trace widths are adjusted on each layer, so that the impedance is identical, the propagation speed of the microstrip is always faster than the strip- line, typically by 13–17%. • e speed of propagation of digital sig- nals is independent of trace geometry and impedance. DESIGN007 Resources • Beyond Design: "Crosstalk Margins," "DDR3/4 Fly-by vs T-Topology Routing," "Signal Flight Time Variance in Multilayer PCBs," by Barry Olney • "Board-level timing analysis," Tech Design Forum Techniques. • "High-speed PCB design timing analysis and simulation strategy," Engineering Technical, PCB- way. • "Understanding Simulation Analysis Parame- ters for DDR4 Bus Systems in SystemSI," Cadence. Barry Olney is managing director of In-Circuit Design Pty Ltd (iCD), Australia, a PCB design service bureau that specializes in board- level simulation. The company developed the iCD Design Integ- rity software incorporating the iCD Stackup, PDN, and CPW Planner. The software can be downloaded at www.icd.com.au. To read past columns, click here.