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AUGUST 2024 I DESIGN007 MAGAZINE 39 Low-cost Adders (<10% board cost) Complex routing and scoring mean a small increase in process time, but a process is still required which will be driven by NC programming; it may limit tool life as a function of diameter. Thicker or thinner PCBs (>0.093" [0.229 mm], <0.030" [0.762 mm]) means a material cost variation but it is minimal. Via plug or button print requires a small process change to the screen-print mask dot. Medium-cost Adders (10–25%) Regarding drilled hole quantity, there is a cost adder for high-density design-driven hole count and process time. With smaller drilled hole size, the small drill diameter (<0.010" [0.254 mm]) limits throughput and stack height. Embedded resistors with Ohmega/Ticer technology will need additional core testing and finished board verification. Non- FR-4 materials, like PTFEs, can be 10 to 20 times the FR-4 cost, and material cost is generally 25–50% of the board cost. Edge plating will have additional processes required prior to plating. High-cost Adders (>25% board cost) Advanced technologies may become "science projects" with industry non-standard processing or materials, or "bleeding edge" technology (<0.003" [0.076 mm] L/S, 1:1 aspect ratio microvias, 0.4 mm BGA technology, etc.). Sequential lamination and complex via structures, as well as metal core or external heat sink requirements, also add cost. If layer count will be >30 layers, the yield impact can be significant. Combination/hybrid material sets can be high-cost adders. Regarding material/panel utilization, test coupons and board size can greatly reduce panel utilization; array configurations reduce panel utilization with unusable real estate; and there may be limited availability of panel sizes. Selective plating means multiple surface fin- ishes or multiple thicknesses, complex processing requirements (e.g., masking), and the yield risk of combining non-standard processes. There are also BOOK EXCERPT The Printed Circuit Designer's Guide to... DFM Essentials Chapter 10: Cost Driver Summary cost adders for line width and spacing below indus- try standards for any given copper weight: • ½-ounce copper: 0.003"/0.003" (0.076 mm x 0.076 mm) • 1-ounce copper: 0.004"/0.004" (0.102 mm x 0.102 mm) • Ultra-high-density interconnects • Sub 1 mil line/space (25 and 15 micron) Understanding the cost drivers in PCB fabrication and early engagement between designer and fabri- cator are crucial elements that lead to cost-effective design success. This chapter was extracted from the newly pub- lished book, The Printed Circuit Designer's Guide to DFM Essentials, now available free from the I-Con- nect007 library.