Issue link: https://iconnect007.uberflip.com/i/1537388
JULY 2025 I DESIGN007 MAGAZINE 15 B E YO N D D ES I G N Signal Integrity • Determine which signals are critical and attach rules to restrict routing and control impedance • Define technology rules: Group signals by bus, component, and technology • Set the minimum spacing to avoid crosstalk for each layer • Ensure consistent spacing and symmetry for differential signals Power Integrity • Ensure the planes are low impedance for stable power delivery and add more planes if necessary • Choose PCB materials with low-loss dielectrics for better high-frequency performance EMC • Minimize routing on the outer layers of the PCB to reduce radiation • Set fanout rules to create BGA breakouts If the design rules are established correctly, the design process should proceed smoothly. How- ever, there are always exceptions to these rules. For example, when using ICs with 0.3 mm pitch BGA packages, you may need to reduce trace widths, clearances, and via stacks to accommo- date routing. There is no one-size-fits-all solution when it comes to design constraints. Nevertheless, having a previous set of rules and reusing them for similar technologies can save time and reduce frustration during setup. Figure 2 illustrates the typical constraints involved in planning and defining a high-speed DDR2 and DDR3 design. These constraints should be established at the schematic level and car- ried through to the layout process. This approach allows the engineer to clearly communicate their intent to the PCB designer, reducing the risk of misinterpretation. Additionally, reusing constraints from a previously proven design not only ensures consistent rules but also minimizes the potential for errors. ▼ F i g u re 2 : C o n st ra i nt s p l a n n i n g at t h e s c h e m at i c l eve l .