Issue link: https://iconnect007.uberflip.com/i/1537388
JULY 2025 I DESIGN007 MAGAZINE 51 C O N N ECT T H E D OTS • The number of lamination cycles » Each cycle adds material, tooling, process- ing time, and QA steps » Reducing build-up cycles can dramatically lower the cost • Via structure type » Stacked microvias require more processing (via fill, planarization) and tighter controls, increasing cost » Staggered microvias are more cost-effective and reliable • Via filling and planarization • Tight tolerances » High aspect-ratio vias, narrow trace/space (<3 mil), and tight annular rings require advanced fabrication techniques and add yield risk • Material selections » High-Tg or low-loss materials can drive up material costs and potentially lead times » Asymmetric stack-ups or non-standard stack-ups add complexity Tips for Design To optimize for manufacturability, yield, and cost: • Minimize lamination cycles: Use fewer HDI layers if possible. Consider 1+N+1 or 2+N+2 instead of 3+N+3 • Use staggered microvias: Reduce via fill complexity and enhance reliability • Balance stack-up symmetry: Minimize warp- age by mirroring dielectric and copper weights • Avoid tight drill-to-copper tolerances: Main- tain generous spacing around vias, espe- cially buried or stacked • Validate via aspect ratios: Keep mechanical and laser vias within fab capability, typically 1:1 or less • Engage early with your fabricator: Co-design the stackup and via structure with the fab shop Conclusion Sequential lamination unlocks the design flexibility needed for HDI products but comes with a steep cost and reliability burden if not well-managed. For PCB design engineers, the key is to design with manufacturing in mind. Reduce unnecessary lam- ination cycles, simplify via structures, and ensure the design team aligns stack-up symmetry and tol- erances with fabrication capabilities. Partnering closely with your PCB fabricator and involving them early in the design phase can mean the difference between a smooth ramp to produc- tion and months of yield-chasing rework. DESIGN007 Matt Stevenson is vice president and general manager of ASC Sunstone Circuits. To read past columns, click here. Download Matt's book, The Printed Circuit Designer's Guide to… Designing for Reality and listen to the podcast here. You can view other titles in the I-007eBooks library.