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22 DESIGN007 MAGAZINE I AUGUST 2025 selected materials and spacing, determine the ideal routing layers. Then, place high-speed com- ponents (clocks, SerDes, DDR) to minimize trace, stub length, and via count on those preferred lay- ers. Pay particular attention to the flight time and skew of the critical signals. It is advisable to partition component groups based on rise-time and operating frequency, posi- tioning the highest-speed devices closest to the connector, as illustrated in Figure 1. Subsequent placement should follow a descending order of signal speed, with analog sections located furthest from the connector to reduce the risk of noise cou- pling into sensitive circuitry. Electrically isolate switch-mode power supplies while maintaining a continuous common ground plane. Special atten- tion should be given to minimizing net crossovers to improve routing efficiency. It is essential that all analog signals are routed within the analog section, while digital signals are confined to the digital section, both sharing a con- tinuous common ground plane. Control signals may traverse between these domains as needed. Over the years, I've employed a proven method to enforce this segregation: route fences or keep-outs. We implement these by placing elongated keep-out zones across signal layers, effectively guiding the routing process and preventing signals from cross- ing designated boundaries on specific layers. Figure 1 illustrates a typical application of this technique. It is important to remember that high-speed return currents follow the path of least inductance. For example, when a trace runs from an analog-to-dig- ital converter (ADC) to an FPGA, the return current will flow directly beneath that trace, avoiding nearby sections. Route fences also help control the auto- router by preventing signals from crossing boundar- ies while allowing control signals to pass through. Since crosstalk is caused by an aggressor signal coupling onto a victim signal, higher aggressor voltages induce more crosstalk. To mitigate this, it is advisable to segregate groups of nets based on their signal amplitudes. This prevents higher voltage nets (such as 3.3V) from affecting lower voltage nets (such as 1.5V), which have reduced noise margins. Signal flight time and skew are critical consid- erations in high-speed PCB design. A primary fac- tor influencing these parameters is the place- ment of components. By controlling the place- ment of devices and assuming adherence to good design practices, the maximum signal delay can be approximated by the longest Manhattan (X + Y) distance within a specific clock domain. Route the clocks/strobes first within a group, without serpen- tine patterns initially. This allows for accurate skew matching later in the process, as nets with higher signal velocity can be lengthened to align with the longest propagation delay, ensuring synchronized signal arrival across all critical paths. The clock should always have the longest delay so the data and address lines have time to set- tle before being clocked. Consequently, flight time and skew for an entire clock domain are deter- mined by the maximum placement and routing rules that enforce trace delay matching. However, there is a sweet spot. If the distance between the B E YO N D D ES I G N ▼ F i g u re 2 : P ro c e s s o r a n d m e m o r y d ev i c e p l a c e m e nt re q u i re m e nt s w i t h 1 . 8V p l a n e.