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A RT I C L E 34 I-CONNECT007 MAGAZINE I JULY 2026 The transition from HDI to every layer intercon- nect (ELIC) is where the DFM gap between design intent and fabrication reality is most visible. Several common misconceptions appear consistently in the data packages we review at ASC. The most common ELIC design mistake mirrors what we generally see in first-time UHDI builds: using process minimums everywhere because they appear on a capability chart. In ELIC, this is espe- cially consequential. If only one region truly requires aggressive geometry, say, a fine-pitch BGA escape, the rest of the design should preserve margin. Relaxing non-critical areas makes the overall build more manufacturable without sacrificing the dense region that drives the stackup. Production capability charts reflect what is achiev- able under controlled conditions. Production intro- duces material variation, panel movement, plating distribution effects, and statistical process spread. ELIC compresses those windows. Small adjust- DFM Mistakes Designers Make When Moving to ELIC BY A N AYA VA R DYA , A M E R I CA N STA N DA R D C I RC U I TS Figure 1: Stacked microvias maximize routing density but introduce a thermal stress column and cumulative void risk at each interface. Staggered vias distribute mechanical load and are the production-stable default. The strategic question is "Should we stack?" not "Can we stack?" Editor's note: This is the second part of an article series on every layer interconnect. Read part one here.