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36 I-CONNECT007 MAGAZINE I JULY 2026 ments, such as widening a via capture pad by a few microns or relaxing a mask dam in a non-critical area, can shift a build from marginal to stable. Via Stacking Rules That Do Not Transfer From HDI Designers who have mastered HDI sometimes carry stacking rules into ELIC without recognizing that aspect ratio and fill requirements change with each additional level. A microvia correctly sized for a two-level stack may not achieve equivalent fill quality in a four-level stack. The target pad must be larger to account for positional uncertainty across multiple build cycles. The 1:1 aspect ratio guideline is the foundational anchor: a 50 µm via requires an approximately 50 µm dielectric. This relationship affects impedance control, copper thickness, lamination cycles, and long-term reliability simultaneously. Designers often miss the guidance that if a design terminates multiple ELIC via structures on external layers, the UHDI circuitry should be moved to internal layers. External layers carry the greatest cumulative registration uncertainty from the full build sequence, and placing multiple via termina- tions there compounds both the registration risk and the solder mask complexity. In Table 1, staggered vias are the production- stable default in ELIC. Stacked vias should be used selectively, only where density requirements leave no alternative. Treating Solder Mask as a Finishing Detail In ELIC, the solder mask directly affects pad defini- tion, isolation, assembly yield, and manufacturabil- ity. When pad openings approach 60 µm and mask dams shrink toward 50 µm, alignment tolerances do not scale proportionally. A layout that looks ac- ceptable in CAD can become difficult to build if the mask strategy assumes more positional precision than the process can comfortably deliver. Designers should evaluate the solder mask strategy before the layout is finalized. Key questions: • Are solder mask-defined (SMD) pads appro- priate for this pitch? • Are narrow dams realistic? Mixing SMD and non-solder mask-defined (NSMD) pads within a single fine-pitch BGA intro- duces variability that creates assembly challenges downstream. Ignoring Thermal Implications of Eliminating Through-holes Designers sometimes choose ELIC to maximize signal routing density without fully modeling the thermal implications of removing through-holes from the heat dissipation path. Through-hole cop- per barrels are effective thermal conductors from components to internal planes. When replaced by an all-microvia architecture, the thermal resistance Table 1: Understanding this gap is foundational to ELIC design. Minimum capability is a process boundary. DESIGN CAPABILITY KEY BENEFIT TRADE-OFF Stacked microvias Maximum routing density Higher cost and complexity; cumulative stress column; void risk at each interface Staggered microvias Superior mechanical reliability; distributed stress load Slightly more routing space required for lateral trace connection